Nitride Semiconductor Chip V-Defect ESD Protection

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Solution Overview

Problem

Nitride semiconductor chips are prone to damage from electrostatic discharges due to high dislocation density in sapphire substrates, leading to leakage currents and reduced light output when protective measures like microdiodes are implemented, which compromise crystal quality.

Innovation Solution

A method involving the creation of V-defects through an etching process during epitaxial growth of nitride semiconductor layers, allowing for ESD protection without compromising crystal quality or light output, by growing layers with specific indium and aluminum content and using MOVPE at controlled temperatures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If microdiodes are integrated into the semiconductor layer sequence to protect from electrostatic discharge damage, then ESD protection is improved, but crystal quality in regions outside the V-defects is reduced, resulting in reduced light output

Engineering Contradiction:
ImproveESD protectionVSAvoidlight output
Core Design Contradiction:
ReliabilityVSIllumination intensity

Solution Approach 1:

The first layer is divided into multiple sublayers with different indium contents, creating a segmented structure that allows V-defects to be confined to specific regions while maintaining high crystal quality in other areas. This segmentation enables the ESD protection function to be localized without compromising the overall light output of the semiconductor chip.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the semiconductor structure are given different properties: the V-defect regions provide ESD protection while the surrounding areas maintain high crystal quality for optimal light emission. The indium content is varied locally in different sublayers to achieve this differentiation of functional zones.

Inventive Principle:
Principle #3Local quality

2Reliability

If growth conditions are modified to create V-defects for ESD protection, then ESD stability is improved, but crystal quality is reduced

Engineering Contradiction:
ImproveESD stabilityVSAvoidcrystal quality
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The growth process is segmented into multiple stages with different conditions. The first layer is grown with specific conditions to initiate V-defects, while subsequent layers are grown with optimized conditions to maintain high crystal quality. This temporal and spatial segmentation of growth conditions allows both ESD protection and high crystal quality to be achieved.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

V-defects are preliminarily created in the first layer before growing the remaining semiconductor layers. This preliminary action ensures ESD protection is established early in the structure, allowing subsequent layers to be grown with focus on maintaining high crystal quality without needing to continuously modify growth conditions.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If an etching process is used to initiate V-defects, then ESD protection is achieved with minimal morphological imperfections, but additional process steps are required

Engineering Contradiction:
ImproveESD protectionVSAvoidprocess steps
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The etching process acts as an intermediary step that selectively removes material to initiate V-defects without causing extensive damage to the crystal structure. This intermediary process enables the creation of ESD protection structures with minimal morphological imperfections, and the use of in-situ etching integrates this step into the existing epitaxial growth equipment.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method produces ESD-stable semiconductor chips with high crystalline quality and maintained light output by embedding V-defects as parallel protection diodes within the quantum film structure, minimizing morphological imperfections and ensuring precise control over layer characteristics.

Implementation Method 1

Layer growth may take place in an epitaxy facility by means of, for example, MOVPE at a predetermined reactor temperature with the addition of precursor gases such as, for example, trimethylgallium, triethylgallium, ammonia and/or hydrogen.

Methodology Applied
Scientific EffectMetal-Organic Chemical Vapor Deposition (MOVPE): Chemical Vapour Deposition

Implementation Method 2

carrying out an etching process to initiate V-defects

Methodology Applied
Scientific EffectChemical Etching:

Implementation Method 3

These V-defects may act as ESD protection diodes connected in parallel with the quantum film structure

Methodology Applied
Scientific EffectElectrostatic Discharge (ESD) protection through microdiode action: Electrostatic Discharge

Data Source

PatentUS10475951B2Optoelectronic semiconductor chip and method for the production thereof
Publication Date: 2019.11.12 OSRAM OLED
  • US10475951B2 patent drawing
  • US10475951B2 patent drawing

AI summary

A method for producing an optoelectronic semiconductor chip is disclosed. A substrate is provided and a first layer is grown. An etching process is carrying out to initiate V-defects. A second layer is grown and a quantum film structure is grown. An optoelectronic semiconductor chip is also disclosed. The method can be used to produce the optoelectronic semiconductor chip.