Nitride Semiconductor Device With Vertical Wire And Insulating Interlayer

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Horizontal power-electronics semiconductor devices with multi-finger structures face challenges in reducing size while maintaining high breakdown field strength and electron mobility, leading to increased parasitic capacitance and switching losses due to large wire sizes.

Innovation Solution

The semiconductor device employs a nitride semiconductor structure with a multi-finger electrode configuration, where the second wire is positioned above the active region, and the first and third wires are on a separate plane, with an insulating interlayer between the nitride semiconductor layer and the second wire, and a specific dielectric constant ratio to minimize parasitic capacitance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If a multi-finger structure with large gate width is used to drive large current, then the driving capability is improved, but the device size is increased

Engineering Contradiction:

Improvedriving capabilityVSAvoiddevice size

Core Design Contradiction:

PowerVSArea of stationary object

Solution Approach 1:

The patent positions the second wire above the active region in a vertical dimension rather than placing it in the same plane as other wires. This three-dimensional wire arrangement allows for more efficient space utilization, reducing the horizontal footprint of the device while maintaining the multi-finger structure's current driving capability.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Reliability

If wire size is increased to connect electrodes, then electrical connection is improved, but parasitic capacitance is increased

Engineering Contradiction:

Improveelectrical connectionVSAvoidparasitic capacitance

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

The patent introduces an insulating interlayer as an intermediary between the nitride semiconductor layer and the second wire. This insulating layer acts as a mediator that electrically isolates the wire from the semiconductor, thereby reducing parasitic capacitance while maintaining reliable electrical connections through the wire's intended connection points.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent specifies that the insulating interlayer has a dielectric constant of 5 or less, which is a parameter change designed to minimize parasitic capacitance. By selecting materials with low dielectric constants and controlling the layer thickness, the patent reduces the capacitive coupling between the wire and the semiconductor layer while preserving electrical connection integrity.

Inventive Principle:

Principle #35Parameter changes

3Productivity

If switching frequency is increased to improve power efficiency, then energy efficiency is improved, but switching losses are increased

Engineering Contradiction:

Improvepower efficiencyVSAvoidswitching losses

Core Design Contradiction:

ProductivityVSLoss of energy

Solution Approach 1:

The patent converts the potentially harmful effect of parasitic capacitance into a beneficial outcome by using the insulating interlayer with low dielectric constant. This reduces the capacitive loading that would normally cause switching losses, thereby enabling high-frequency operation with reduced energy loss. The insulating layer transforms what would be a parasitic effect into a controlled design feature that supports high-frequency switching.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration results in a smaller semiconductor device with reduced parasitic capacitance, lower source resistance, and improved high-frequency performance by maintaining high electron mobility and breakdown field strength.

Implementation Method 1

there is demand for a decrease in size... this configuration results in a smaller semiconductor device with reduced parasitic capacitance

Methodology Applied

Scientific EffectParasitic capacitance: Capacitance

Implementation Method 2

Nitride-based semiconductor materials have high breakdown field strength and high electron mobility

Methodology Applied

Scientific EffectElectron mobility: Conduction (electrical)

Implementation Method 3

with an insulating interlayer between the nitride semiconductor layer and the second wire, and a specific dielectric constant ratio to minimize parasitic capacitance

Methodology Applied

Scientific EffectDielectric constant: Dielectric Permittivity

Data Source

PatentUS10109715B2Semiconductor device

Publication Date: 2018.10.23 KK TOSHIBA

AI summary

A semiconductor device according to an embodiment includes: a substrate having a first plane and a second plane provided on the opposite side of the first plane; a first nitride semiconductor layer provided on the first plane; source electrodes provided on the first nitride semiconductor layer; drain electrodes provided on the first nitride semiconductor layer, each of the drain electrodes provided between the source electrodes; gate electrodes provided on the first nitride semiconductor layer, each of the gate electrodes provided between each of the source electrodes and each of the drain electrodes; a first wire provided on the second plane and electrically connected to the source electrodes; a second wire electrically connected to the drain electrodes; a third wire provided on the second plane and electrically connected to the gate electrodes; and an insulating interlayer provided between the first nitride semiconductor layer and the second wire.