Nitride Spacer Structure for 3D Memory Film Quality

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Solution Overview

Problem

The integration degree of two-dimensional semiconductor devices is limited due to the need for expensive equipment for pattern downsizing, and three-dimensional semiconductor memory devices face challenges in maintaining film quality during high-temperature processes.

Innovation Solution

A semiconductor device design incorporating vertical structures with spacers having varying nitride concentrations to minimize stress during high-temperature processes, featuring a substrate with electrode structures, bit lines, vertical semiconductor patterns, and spacers with different nitride regions to enhance integration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If three-dimensional semiconductor memory devices are used to increase integration density, then integration degree is improved, but film quality deteriorates due to high-temperature processes

Engineering Contradiction:
Improveintegration densityVSAvoidfilm quality
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The spacer is designed with a non-uniform nitride concentration distribution, having a first nitride region with higher nitride concentration adjacent to the common source plug and a second nitride region with lower nitride concentration farther from the plug. This local quality variation allows the spacer to provide stress compensation exactly where needed (near the plug) while maintaining overall structural integrity, thereby resolving the contradiction between achieving high integration density through 3D structures and maintaining film quality during high-temperature processing.

Inventive Principle:
Principle #3Local quality

2Manufacturing precision

If expensive equipment is used for pattern downsizing in two-dimensional devices, then manufacturing precision is improved, but device complexity and cost increase

Engineering Contradiction:
Improvepattern downsizing capabilityVSAvoidequipment requirement
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent transitions from two-dimensional planar device structures to three-dimensional vertically stacked structures. By stacking multiple memory cells vertically, the device achieves higher integration density without requiring further pattern downsizing in the lateral plane. This dimensional transition eliminates the need for expensive lithography equipment while maintaining manufacturing precision, as the vertical stacking can be achieved through standard deposition and etching processes.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The design allows for increased integration density while maintaining film quality, reducing the need for expensive equipment and improving manufacturing efficiency.

Implementation Method 1

performing a nitridation process at a surface of the spacer; through the nitridation process, the spacer is formed with a first nitride region disposed adjacent to the common source plug while having a nitride (N) concentration of b (%) to a (%) (a>b)

Methodology Applied
Scientific EffectNitridation: Nitriding

Data Source

PatentUS12568620B2Semiconductor device including nitride spacers
Publication Date: 2026.03.03 SAMSUNG ELECTRONICS CO LTD
  • US12568620B2 patent drawing
  • US12568620B2 patent drawing
  • US12568620B2 patent drawing

AI summary

A semiconductor device comprising: a substrate; an electrode structure disposed on the substrate while extending in a first direction, the electrode structure including a plurality of electrodes stacked in a second direction which is a vertical direction of the substrate; a bit line disposed on the electrode structure; vertical structures extending through the electrode structure in the second direction and contacting the substrate, each of the vertical structures including a vertical semiconductor pattern electrically connected to the bit line, and a data storage pattern surrounding a side wall of the vertical semiconductor pattern; common source plugs extending through the electrode structure in the second direction and contacting the substrate under a condition that the vertical structures are disposed among the common source plugs; and spacers respectively disposed to surround side walls of the common source plugs, each of the spacers including regions respectively having different nitride (N) concentrations.