Nitride Spacer Trim-Back for Gate Isolation and Silicide Quality
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Solution Overview
Problem
The increasing complexity and miniaturization of semiconductor integrated circuits lead to narrower spaces between gate stacks, resulting in degraded silicide quality and poor contact yield due to high resistivity and aspect ratios, necessitating a method to increase the distance between gate stacks while maintaining process control.
Innovation Solution
A method for trimming back nitride spacers in the replacement gate process, which includes forming nitride spacers, performing source and drain implants, and selectively trimming back the spacers to widen the space between gate structures, allowing for proper silicide formation and improved contact yield, while using a hard mask to protect polysilicon and high-K dielectric layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If spacers are formed on the sidewalls of gate stacks to isolate gate stacks from neighboring silicide regions, then gate stack isolation is improved, but the space between gate stacks becomes narrower
Solution Approach 1:
The spacer formation process is segmented into multiple stages: initial spacer formation for isolation, followed by selective removal in specific regions, and subsequent re-formation or adjustment. This allows different regions to have different spacer configurations - full spacers for isolation where needed, and reduced/no spacers where space is required for silicide formation.
Solution Approach 2:
The spacer structure is made non-uniform across different regions of the substrate. In some regions, spacers are formed to provide isolation, while in other regions, spacers are selectively removed or not formed to maintain adequate space for silicide formation. This local differentiation resolves the contradiction between needing isolation and needing space.
2Productivity
If the space between gate stacks is reduced to increase circuit density, then more circuits can be integrated, but silicide quality degrades due to high aspect ratio
Solution Approach 1:
The spacer thickness is made dynamic rather than uniform across the entire substrate. Through selective etching or selective formation processes, the spacer thickness varies by region - thinner or absent in areas requiring silicide formation, and thicker in areas requiring isolation. This dynamic adjustment allows adequate space for silicide formation while maintaining high circuit density elsewhere.
Solution Approach 2:
The spacer structure is preliminarily formed to provide isolation, then selectively modified in subsequent steps to create openings or reduce thickness in specific regions before silicide formation. This preliminary formation followed by selective modification allows the process to benefit from both the isolation provided by spacers and the space required for quality silicide formation.
3Manufacturing precision
If nitride spacers are trimmed back to increase space between gate structures, then silicide formation quality improves, but polysilicon above high-K dielectric may be exposed and silicided
Solution Approach 1:
An intermediary protective layer or structure is introduced to shield the polysilicon above the high-K dielectric during the spacer trim-back process. This could be a remaining portion of the original spacer material, a newly deposited protective layer, or a combination thereof. The intermediary protects the polysilicon from unintended siliciding while allowing the spacer trim-back to proceed to improve silicide formation quality in other regions.
Solution Approach 2:
Protective measures are taken in advance before the spacer trim-back process to prevent exposure of the polysilicon. The protective layer or structure is formed or positioned beforehand to counteract the potential harmful effect of spacer removal. This preliminary anti-action ensures that even if spacers are trimmed back significantly, the polysilicon remains protected from siliciding.
Data Source
AI summary
The embodiments of methods described in this disclosure for trimming back nitride spacers for replacement gates allows the hard mask layers (or hard mask) to protect the polysilicon above the high-K dielectric during trim back process. The process sequence also allows determining the trim-back amount based on the process uniformity (or control) of nitride deposition and nitride etchback (or trimming) processes. Nitride spacer trim-back process integration is critical to avoid creating undesirable consequences, such as silicided polyisicon on top of high-K dielectric described above. The integrated process also allows widening the space between the gate structures to allow formation of silicide with good quality and allow contact plugs to have sufficient contact with the silicide regions. The silicide with good quality and good contact between the contact plugs and the silicide regions increase the yield of contact and allows the contact resistance to be in acceptable and workable ranges.