Nitride Semiconductor Substrate Warp Control via Offset Angle
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Solution Overview
Problem
Thick nitride semiconductor layers on Si substrates face challenges with warp and crack generation due to thermal expansion coefficient differences and crystal lattice mismatches, especially in large diameter substrates, making it difficult to maintain crystallinity and evenness for high withstand voltage power devices.
Innovation Solution
A nitride semiconductor substrate with a Si single crystal substrate having a specific offset angle of 0.1° to 1° with respect to the (111) plane, combined with a buffer layer and semiconductor active layer of group 13 nitrides, and a SiO2 film on the back, which controls warp and crack generation by managing dopant concentration and stress distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a nitride semiconductor layer is epitaxially grown on a Si single crystal substrate at high temperature, then the device property is improved, but cracks and crystal defects are generated due to thermal expansion coefficient difference and crystal lattice mismatch
Solution Approach 1:
A buffer layer comprising group 13 nitride is introduced between the nitride semiconductor layer and the Si single crystal substrate. This buffer layer acts as an intermediary that accommodates the crystal lattice mismatch and thermal expansion coefficient difference between the nitride semiconductor and Si substrate, preventing crack generation and crystal defects while enabling high temperature epitaxial growth for improved device properties
Solution Approach 2:
The patent employs a composite structure consisting of multiple layers: a Si single crystal substrate, a buffer layer comprising group 13 nitride, and a nitride semiconductor layer. This composite material structure allows each layer to serve its specific function - the Si substrate provides mechanical support, the buffer layer mitigates lattice mismatch, and the nitride semiconductor layer provides the desired semiconductor properties, thereby resolving the contradiction between device property improvement and crack resistance
2Reliability
If the nitride layer is thickened to achieve high withstand voltage (greater than 4 μm), then the withstand voltage capability is improved, but cracks and warp are generated in the nitride semiconductor substrate
Solution Approach 1:
The buffer layer comprising group 13 nitride serves as a mediator that distributes and reduces the stress generated by thick nitride layers. By introducing this intermediate layer, the patent enables the formation of thick nitride layers (4-10 μm) required for high withstand voltage applications while preventing the generation of cracks and warp in the substrate
Solution Approach 2:
The patent specifies precise parameter ranges for the Si single crystal substrate, including offset angle (0.1° to 1° or −1° to −0.1° with respect to (111) plane) and average dopant concentration (1×10¹⁸ to 1×10²¹ cm⁻³), to optimize stress distribution and prevent warp and crack generation in thick nitride layers, thereby enabling high withstand voltage capability without compromising substrate stability
3Manufacturing precision
If a Si single crystal substrate with small offset angle is used to maintain good crystallinity, then the crystallinity of the nitride layer is improved, but it becomes difficult to control warp in large diameter substrates
Solution Approach 1:
The patent identifies and optimizes specific parameter ranges for the Si single crystal substrate, including offset angle (0.1° to 1° or −1° to −0.1° with respect to (111) plane) and average dopant concentration (1×10¹⁸ to 1×10²¹ cm⁻³), to simultaneously achieve good crystallinity of the nitride layer and effective warp control in large diameter substrates
Solution Approach 2:
The buffer layer comprising group 13 nitride acts as an intermediary that decouples the relationship between substrate offset angle and nitride layer crystallinity. This allows the use of substrates with optimized offset angles for warp control while the buffer layer ensures good crystallinity of the nitride layer is achieved
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively controls warp and crack generation while maintaining good crystallinity and evenness of the nitride semiconductor layer, enabling the use of the substrate for high withstand voltage power devices with thick nitride layers.
Implementation Method 1
since a nitride semiconductor has a thermal expansion coefficient larger than that of a Si single crystal, a nitride semiconductor layer epitaxially grown on a Si single crystal substrate at a high temperature may generate a crack, a crystal defect due to difference in crystal-lattice constant from Si when it is cooled to room temperature
Implementation Method 2
Such problems are conventionally addressed by reducing stress by means of a multilayered buffer layer
Data Source
AI summary
A nitride semiconductor substrate is provided which is suitable for a high withstand voltage power device and prevents a warp and a crack from generating in a Si substrate when forming a thick nitride semiconductor layer on the substrate. A nitride semiconductor substrate 1 is prepared in such a manner that a buffer layer 3 and a semiconductor active layer 4 each comprising a group 13 nitride are stacked one by one on one principal plane of a Si single crystal substrate, the one principal plane has an offset angle of 0.1° to 1° or −1° to −0.1° with respect to a (111) plane, an average dopant concentration in a bulk is 1×1018 to 1×1021 cm−3, the Si single crystal substrate 2 has a SiO2 film on the back, and the total thickness of the buffer layer 3 and the semiconductor active layer 4 is 4 to 10 μm.