Nitride Semiconductor Substrate Patterning for Warpage Reduction
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Solution Overview
Problem
Nitride semiconductor substrates face challenges with high dislocation defects and warpage due to lattice mismatch and thermal expansion differences with substrates, limiting their practical use in devices like LEDs and LDs.
Innovation Solution
A method involving the growth of a first nitride semiconductor layer with a specific pattern on a substrate, followed by a second nitride semiconductor layer using the first layer as a growth nucleus, where the pattern features concave and convex portions aligned with the (11-20) plane, reducing dislocations and stress, and minimizing warpage by facet growth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a nitride semiconductor layer is grown on a different type of substrate (sapphire, silicon carbide, spinel, or silicon), then the number of dislocation defects is reduced, but stress is produced within the nitride semiconductor layer due to lattice constant and thermal expansion differences, causing warpage in a freestanding state
Solution Approach 1:
The substrate surface is divided into multiple patterns (stripes, triangles, hexagons, or quadrangles) before growing the nitride semiconductor layer. This segmentation allows the layer to be grown in discrete regions that can better accommodate stress, reducing overall warpage while maintaining low dislocation densities in each segment
Solution Approach 2:
Different regions of the substrate are given different local structures through patterning. The patterns create local variations in stress distribution, allowing each region to better accommodate the lattice mismatch and thermal expansion differences between the substrate and nitride semiconductor layer
2Manufacturing precision
If a striped pattern is used on the substrate, then dislocation defects are reduced to some extent, but dislocations are still generated along the plane joints that occur linearly on the substrate, limiting further reduction
Solution Approach 1:
The invention transitions from symmetric linear stripe patterns to asymmetric triangular, hexagonal, or quadrangular patterns. These geometric shapes create non-linear plane joints that better distribute and redirect dislocation paths, preventing the accumulation of dislocations along straight lines and achieving superior dislocation reduction
3Device complexity
If regular triangular or regular hexagonal openings are used in the pattern, then the structure is simplified, but dislocations still occur along the plane joints at vertex portions where sides intersect
Solution Approach 1:
While maintaining the simplicity of regular geometric shapes, the invention strategically positions and orients these shapes to create asymmetric stress distribution at the vertices. The patterns are arranged to minimize dislocation accumulation at intersection points while preserving the overall geometric simplicity for ease of manufacturing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces dislocation defects and warpage, enhancing the characteristics of grown elements and simplifying chip production by dispersing stress within the substrate.
Implementation Method 1
growing a first nitride semiconductor on a substrate
Implementation Method 2
growing a second nitride semiconductor layer, using a plane equivalent to the (11-20) plane in the first nitride semiconductor pattern as a growth nucleus
Data Source
AI summary
A method for manufacturing a nitride semiconductor substrate includes the steps of growing a first nitride semiconductor on a substrate, patterning the first nitride semiconductor to obtain a pattern surrounded by a plane equivalent to the (11-20) plane and having at least two concave portions that are similar in their planar shape, and growing a second nitride semiconductor layer, using a plane equivalent to the (11-20) plane in the first nitride semiconductor pattern as a growth nucleus.