Nitride Semiconductor Template with Si Gradient for LED
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Solution Overview
Problem
Nitride semiconductor templates for light-emitting diodes face challenges in achieving low resistance and good crystalline characteristics, as increasing impurity levels to reduce resistance can deteriorate crystalline quality and lead to dopant diffusion issues, affecting brightness and reliability.
Innovation Solution
The use of island growth methods and a Si-doped layer with a concentration gradient in the nitride semiconductor template, combined with an O-doped layer, reduces dislocation density and dopant diffusion, maintaining crystalline quality while lowering resistance, and the HVPE method is employed for rapid growth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the amount of impurity to be added is increased to increase carrier concentration, then resistance is reduced, but crystalline characteristics deteriorate
Solution Approach 1:
The patent applies local quality by creating a Si-doped layer with a concentration gradient where the carrier concentration varies through the layer thickness. The carrier concentration is set to be not less than 1×10^17 cm^-3 and not more than 5×10^17 cm^-3 at the outermost surface, with higher concentrations toward the interior. This gradient structure allows different regions of the same layer to have different doping levels, enabling low resistance at the bulk while maintaining good crystalline quality at the surface interface with the light-emitting layer.
2Reliability
If the amount of impurity to be added is increased to reduce resistance, then forward voltage is reduced, but dopant diffusion into the light-emitting portion increases
Solution Approach 1:
The patent applies parameter changes by implementing a carrier concentration gradient in the Si-doped layer. The carrier concentration is controlled to decrease toward the outermost surface (where it is not less than 1×10^17 cm^-3 and not more than 5×10^17 cm^-3) and increase toward the interior. This parameter variation creates a concentration gradient that acts as a barrier to dopant diffusion into the light-emitting layer while still providing sufficient carriers to reduce forward voltage in the bulk region.
3Manufacturing precision
If the thickness of the GaN layer is increased to improve crystalline characteristics, then manufacturing time is reduced by using HVPE method, but the complexity of the growth process increases
Solution Approach 1:
The patent applies mechanics substitution by replacing the conventional MOVPE growth method with the HVPE (Hydride Vapor Phase Epitaxy) method for growing the GaN layer. HVPE provides a much faster growth rate (not less than 10 μm/hr and not more than 100 μm/hr) compared to typical MOVPE rates (several μm/hr), enabling the formation of thick GaN layers (4-10 μm) with good crystalline characteristics in significantly reduced time, thus substituting a slower mechanical growth process with a faster chemical vapor phase process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a nitride semiconductor template with low resistance and improved crystalline characteristics, enabling high-brightness, reliable light-emitting diodes with reduced manufacturing costs.
Implementation Method 1
One of crystal growth methods of such nitride semiconductor materials is a Hydride Vapor Phase Epitaxy (HVPE) method in which metal chloride gas and ammonia are used as raw materials
Implementation Method 2
when the impurity amount is large, brightness is reduced due to dopant diffusion into a light-emitting portion, especially into an active layer, formed on the template
Data Source
AI summary
A nitride semiconductor template includes a substrate, and a group III nitride semiconductor layer formed on the substrate and including a Si-doped layer doped with Si as an uppermost layer thereof. The group III nitride semiconductor layer has a total thickness of not less than 4 μm and not more than 10 μm. The Si-doped layer includes a Si concentration gradient layer having a carrier concentration that gradually decreases toward an outermost surface thereof so as to be not less than 1×1017 cm−3 and not more than 5×1017 cm−3 at the outermost surface of the group III nitride semiconductor layer.