Nitride-Based Transistor Leakage Current Suppression Structure
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Solution Overview
Problem
Nitride-based transistors, particularly gallium nitride (GaN) transistors, face limitations in carrier mobility and breakdown voltage due to electric field concentration at gate electrodes and leakage current issues caused by defect sites at the interface between nitride-based semiconductor layers and passivation layers, which degrade their high voltage characteristics.
Innovation Solution
The implementation of a nitride-based transistor structure that includes a semiconductor structure with doped nitride-based layers and a leakage current suppression structure featuring a depletion layer, either in the nitride-based semiconductor layers or in trenches, to reduce leakage current by trapping and recombining electric charges at defect sites.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If annealing process is performed at temperature over 600 degrees Celsius to reduce defect sites, then defect site density is reduced, but leakage current is still not sufficiently suppressed
Solution Approach 1:
A dedicated leakage current suppression structure is introduced as an intermediary component between the source/drain electrodes and the substrate. This structure specifically targets and suppresses leakage current paths without requiring extreme thermal processing, thereby solving the leakage issue while avoiding the manufacturing complexity of high-temperature annealing.
Solution Approach 2:
The invention changes the approach from thermal parameter modification (annealing at >600°C) to structural parameter modification by introducing a suppression structure with specific electrical properties. This structural change directly addresses leakage current without the need for extreme temperature processing.
2Ease of manufacture
If planar-type configuration is used, then fabrication is simplified, but carrier mobility is limited due to electric field disturbance at channel surface
Solution Approach 1:
The invention transitions from a two-dimensional planar channel configuration to a three-dimensional vertical channel configuration. This dimensional change allows carriers to move vertically through the channel, avoiding the surface electric field disturbances that limit mobility in planar devices, while maintaining fabrication feasibility through vertical growth processes.
Solution Approach 2:
The patent employs composite material structures including multiple nitride semiconductor layers with different compositions and doping types (n-type, p-type, and undoped regions). This composite structure enables simultaneous optimization of carrier mobility in the vertical channel and suppression of leakage current through the depleted regions.
3Ease of manufacture
If planar-type GaN transistors are used, then fabrication is easier, but breakdown voltage characteristic is degraded due to electric field concentration at gate electrode corners
Solution Approach 1:
The invention adopts a vertical transistor configuration where the channel extends in the vertical dimension rather than horizontally. This eliminates the corner regions of planar gate electrodes where electric field concentration occurs, thereby improving breakdown voltage while maintaining fabrication simplicity through vertical processing techniques.
Solution Approach 2:
The patent changes the geometric parameters of the transistor structure from planar to vertical configuration. This parameter change redistributes the electric field more uniformly, preventing concentration at sharp corners and thereby enhancing breakdown voltage characteristics without complicating the fabrication process.
4Reliability
If defect sites at interface are not suppressed, then manufacturing is simpler, but leakage current increases and high voltage characteristic is degraded
Solution Approach 1:
A leakage current suppression structure is introduced as an intermediary element that specifically addresses the interface defect issue. This structure acts as a barrier to leakage current paths without requiring complex multi-layer interface engineering, thereby improving high voltage characteristics while limiting structural complexity.
Solution Approach 2:
The invention applies local quality enhancement by introducing the suppression structure only in regions where leakage current is most problematic (near the substrate interface and electrode regions). This localized approach improves high voltage characteristics without unnecessarily complicating the entire device structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses leakage current, enhancing the high voltage characteristics of nitride-based transistors by reducing parasitic current paths and improving carrier mobility and breakdown voltage.
Implementation Method 1
The leakage current suppression structure includes a depletion layer in at least one of the first and third nitride-based semiconductor layers
Implementation Method 2
to reduce leakage current by trapping and recombining electric charges at defect sites
Data Source
AI summary
A nitride-based transistor includes a semiconductor structure, a gate electrode and a leakage current suppression structure. The semiconductor structure includes a first nitride-based semiconductor layer doped with impurities of a first conductivity type, a second nitride-based semiconductor layer doped with impurities of a second conductivity type, and a third nitride-based semiconductor layer doped with impurities of the first conductivity type. The gate electrode overlaps the second nitride-based semiconductor layer. The leakage current suppression structure is disposed along edges of the semiconductor structure. The leakage current suppression structure includes a depletion layer in at least one of the first and third nitride-based semiconductor layers.