Group III Nitride Wafer Planarization for Bow-Resistant Mesas

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Solution Overview

Problem

Current methods for fabricating semiconductor wafers with Group III nitride layers for power electronic applications face challenges in achieving planarization and surface uniformity, leading to issues with wafer bow and fragility during processing.

Innovation Solution

A method involving the deposition of an insulating layer on a substrate with mesas of epitaxial Group III nitride layers, followed by chemical mechanical polishing to produce a planarized surface, where the insulating layer is selectively removed to create a structured mask and protrusions, allowing for the formation of discrete mesas and a passivation layer to support transistor devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional fabrication methods are used for Group III nitride layers, then transistor devices can be formed, but surface planarity and uniformity deteriorate, causing wafer bow and fragility

Engineering Contradiction:
Improvesurface planarityVSAvoidwafer fragility
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

An insulating layer is deposited over the Group III nitride layers before final processing, serving as a protective and planarizing element. This preliminary action prevents wafer bow and fragility during subsequent fabrication steps by providing mechanical support and a planar surface for further processing

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The method employs selective removal of the insulating layer to create mesas with controlled geometry. By changing the physical state and configuration of the insulating layer through selective etching and chemical mechanical polishing, the surface planarity is improved while maintaining structural integrity

Inventive Principle:
Principle #35Parameter changes

2Reliability

If insulating layer is deposited to protect mesas, then wafer bow is reduced, but additional processing steps are required to achieve final surface planarity

Engineering Contradiction:
Improvewafer bow controlVSAvoidprocessing steps
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The insulating layer serves multiple functions simultaneously: it protects the mesas during fabrication, reduces wafer bow, and provides a surface that can be planarized through chemical mechanical polishing. By combining these functions into a single layer, the overall process complexity is reduced despite the additional deposition step

Inventive Principle:
Principle #5Merging (Combining)

3Ease of manufacture

If selective removal of insulating layer is performed to create mesas, then discrete device regions are formed, but precision control of mesa geometry is required

Engineering Contradiction:
Improvemesa formationVSAvoidmesa geometry control
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The insulating layer acts as an intermediary material that simplifies mesa formation. Instead of directly etching the Group III nitride layers, the insulating layer is selectively removed to define mesa regions, providing a buffer that makes geometry control more manageable and less precise direct etching requirements

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach results in a highly planarized surface with reduced wafer bow, enabling improved handling and processing of semiconductor wafers, with surface planarity variation less than ±10% of the mesa height over a 200mm diameter, and supports the formation of high-voltage transistor devices with low on-resistance and efficient power switching.

Implementation Method 1

progressively removing portions of the insulating layer by chemical mechanical polishing to produce a planarised surface

Methodology Applied
Scientific EffectChemical mechanical polishing:

Implementation Method 2

a stack of epitaxial Group III nitride layers for a transistor device

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Data Source

PatentEP3300100B1Semiconductor wafer and method for fabricating a semiconductor wafer
Publication Date: 2024.01.03 INFINEON TECHNOLOGIES AG
  • EP3300100B1 patent drawingFigure 1~2
  • EP3300100B1 patent drawingFigure 3
  • EP3300100B1 patent drawingFigure 4

AI summary

In an embodiment, a method of planarising a surface includes applying a first layer to a surface including a protruding region such that the first layer covers the surface and the protruding region, removing a portion of the first layer above the protruding region and forming an indentation in the first layer above the protruding region, the protruding region remaining covered by material of the first layer, and progressively removing an outermost surface of the first layer to produce a planarised surface.