Nitrided High-K Gate Dielectric for Metal FETs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The scaling of MOSFETs is limited by the thickness of SiO2 gate dielectrics, and high-k dielectric materials face challenges due to the growth of low dielectric constant SiO2-like interface layers, affecting the electrical performance of hafnium-based gate stacks.
Innovation Solution
A method involving the formation of a gate structure with a nitrided high-k gate dielectric and metal gate conductor, where a nitrogen-based plasma is applied to the gate dielectric and metal gate conductor, allowing for the deposition of a second metal gate conductor directly on the nitrided gate dielectric, which improves the threshold voltage and work function for n-type and p-type semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Force
If high-k dielectric materials are used to increase dielectric constant, then equivalent oxide thickness is improved, but low dielectric constant SiO2-like interface layer growth occurs
Solution Approach 1:
A nitrogen-containing dielectric layer is introduced as an intermediary between the high-k dielectric material and the silicon substrate. This intermediate layer prevents the thermodynamically favored growth of low dielectric constant SiO2-like interface layers while maintaining the high dielectric constant properties of the high-k material, thus resolving the contradiction between achieving high dielectric constant and preventing harmful interface layer formation.
Solution Approach 2:
The gate dielectric stack is formed as a composite structure combining multiple materials: a nitrogen-containing dielectric layer and a high-k dielectric material. This composite approach allows the system to benefit from both the interface stability provided by the nitrogen-containing layer and the high dielectric constant of the high-k material, overcoming the limitations of using either material alone.
2Speed
If gate dielectric thickness is reduced to improve device performance, then switching speed is improved, but tunneling leakage currents increase
Solution Approach 1:
The gate dielectric is constructed as a composite stack with a nitrogen-containing dielectric layer and a high-k dielectric material. This composite structure enables the use of a thicker overall dielectric layer that provides equivalent electrical performance to thinner SiO2, thereby reducing tunneling leakage currents while maintaining fast switching speed through the high dielectric constant of the high-k material.
Solution Approach 2:
The invention changes the dielectric parameter by introducing high-k dielectric materials with dielectric constants greater than SiO2 into the gate stack. This parameter change allows the system to achieve the same electrical performance with a thicker physical layer, thereby reducing tunneling leakage while maintaining switching speed.
3Length of moving object
If SiO2 gate dielectric thickness is reduced to scale devices, then device feature size is reduced, but electrical performance deteriorates
Solution Approach 1:
The invention changes the dielectric constant parameter by introducing high-k dielectric materials into the gate stack. This allows the system to maintain acceptable electrical performance with reduced gate dielectric thickness, enabling continued device scaling while preserving electrical characteristics.
Solution Approach 2:
A composite gate dielectric structure combining nitrogen-containing dielectric layer and high-k dielectric material is employed. This composite approach enables thinner overall gate dielectric thickness for scaled devices while maintaining electrical performance through the high dielectric constant properties of the high-k material.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances device performance by mitigating device dimension-dependent regrowth and achieving desirable threshold voltages, improving the electrical characteristics of both n-type and p-type FETs.
Implementation Method 1
nitriding the gate dielectric that is present in the first conductivity type region and the first metal gate conductor that is present in the second conductivity type region
Implementation Method 2
a nitrogen-based plasma is applied to the gate dielectric and metal gate conductor
Data Source
AI summary
The present invention, in one embodiment, provides a method of forming a semiconductor device that includes providing a substrate including a first conductivity type region and a second conductivity type region; forming a gate stack including a gate dielectric atop the first conductivity type region and the second conductivity type region of the substrate and a first metal gate conductor overlying the high-k gate dielectric; removing a portion of the first metal gate conductor that is present in the first conductivity type region to expose the gate dielectric present in the first conductivity type region; applying a nitrogen based plasma to the substrate, wherein the nitrogen based plasma nitrides the gate dielectric that is present in the first conductivity type region and nitrides the first metal gate conductor that is present in the second conductivity type region; and forming a second metal gate conductor overlying at least the gate dielectric that is present in the first conductivity type region.