Nitrided Silicon Spacer Reduces Parasitic Capacitance
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Solution Overview
Problem
As semiconductor devices become more highly integrated, the interval between conductive patterns decreases, leading to increased crosstalk and parasitic capacitance between adjacent conductive patterns, which can disrupt signal flow and reduce bit line sensing margin, particularly in memory devices.
Innovation Solution
A method of forming semiconductor devices involves depositing a base layer and a silicon layer on a substrate, followed by a nitridation process to create a nitrided silicon layer with a higher silicon concentration, which is used to form spacer structures with a lower dielectric constant to reduce parasitic capacitance between conductive patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the interval between conductive patterns is decreased to achieve higher integration, then device integration is improved, but parasitic capacitance increases
Solution Approach 1:
A nitrided silicon layer is introduced as an intermediary material between adjacent conductive patterns (bit lines). This intermediate layer has a lower dielectric constant than conventional insulating materials, thereby reducing the parasitic capacitance formed between closely-spaced conductive patterns while maintaining the benefits of high device integration.
Solution Approach 2:
The dielectric constant parameter of the insulating layer between conductive patterns is changed by using a nitrided silicon layer instead of conventional insulating materials. This parameter change (lower dielectric constant) directly reduces the parasitic capacitance between adjacent bit lines, solving the problem of signal interference in highly integrated devices.
2Productivity
If the interval between conductive patterns is decreased to achieve higher integration, then device integration is improved, but crosstalk increases
Solution Approach 1:
The nitrided silicon layer serves as a mediator between adjacent conductive patterns, reducing the electromagnetic coupling and signal interference (crosstalk) between closely-spaced bit lines through its lower dielectric constant property.
3Object-generated harmful factors
If a nitrided silicon layer is formed to reduce parasitic capacitance, then parasitic capacitance is reduced, but process complexity increases
Solution Approach 1:
The formation of the nitrided silicon layer is merged with existing process steps. The base layer and silicon layer are deposited using standard CVD equipment, and the nitridation is performed using existing nitridation chambers, combining multiple functions into integrated process modules to minimize the increase in process complexity.
Solution Approach 2:
The nitrided silicon layer formation process is designed to be multi-functional, serving both as an insulating layer between conductive patterns and as a structural element in the semiconductor device. This multi-functionality reduces the need for additional dedicated process steps, thereby limiting the increase in overall process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach effectively reduces parasitic capacitance and enhances the bit line sensing margin, improving the performance of semiconductor devices by minimizing crosstalk and maintaining signal integrity.
Implementation Method 1
A base layer may be formed on the loaded semiconductor substrate by performing a base deposition process using a base source material
Implementation Method 2
A first silicon layer may be formed on the base layer to a greater thickness than the base layer by performing a first silicon deposition process using a silicon source material different from the base source material
Implementation Method 3
A first nitrided silicon layer may be formed by nitriding the first silicon layer using a first nitridation process
Data Source
AI summary
Provided is a method of forming a semiconductor device. The method can include loading a semiconductor substrate into semiconductor equipment. A base layer can be formed on the loaded semiconductor substrate by performing a base deposition process using a base source material. A first silicon layer can be formed on the base layer to a greater thickness than the base layer by performing a first silicon deposition process using a silicon source material different from the base source material. A first nitrided silicon layer can be formed by nitriding the first silicon layer using a first nitridation process. The semiconductor substrate having the first nitrided silicon layer can be unloaded from the semiconductor equipment.