Nitridized Oxide Tunneling Layer for SONOS Memory
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Solution Overview
Problem
Conventional SONOS-type nonvolatile trapped-charge memory devices face challenges in scaling down programming and erase times while maintaining low operating voltages, as reducing the equivalent oxide thickness of the tunneling layer leads to increased erase and program decay rates and reduced memory window.
Innovation Solution
Incorporating a nitridized oxide tunneling layer with a tailored nitrogen concentration profile, which increases the dielectric constant and reduces trap density at the substrate interface, allowing for lower programming and erase voltages without compromising charge retention, achieved through a multi-step nitridation and oxidation process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the equivalent oxide thickness of the tunneling layer is reduced to enable lower programming voltages, then device scalability and compatibility with low-voltage CMOS are improved, but the erase and program decay rates increase and memory window is reduced
Solution Approach 1:
The patent changes the chemical composition parameters of the tunneling layer by incorporating nitrogen into silicon oxide to form silicon oxynitride. This compositional parameter change increases the dielectric constant of the tunneling layer, allowing for reduced equivalent oxide thickness while maintaining the necessary electrical properties for charge retention and tunneling efficiency at lower voltages.
Solution Approach 2:
The patent creates a composite material by combining silicon oxide with nitrogen to form silicon oxynitride. This composite structure provides the benefits of both materials: the oxide component maintains good interface properties and charge retention, while the nitrogen component increases the dielectric constant, enabling thinner effective oxide thickness for lower operating voltages.
2Ease of manufacture
If conventional oxide tunneling layers are used with reduced thickness, then manufacturing simplicity is maintained, but trap density at the substrate interface increases and memory performance deteriorates
Solution Approach 1:
The patent modifies the chemical composition of the tunneling layer by incorporating nitrogen, which changes the material properties to reduce interface trap density. This compositional parameter change allows for better interface quality without complicating the manufacturing process, as nitrogen incorporation can be achieved through standard semiconductor processing techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The nitridized oxide tunneling layer enables SONOS-type devices to operate with reduced program/erase voltages while maintaining charge retention and threshold levels comparable to conventional devices, enhancing scalability and compatibility with low-voltage CMOS technology.
Implementation Method 1
Incorporating a nitridized oxide tunneling layer with a tailored nitrogen concentration profile, which increases the dielectric constant
Implementation Method 2
a tailored nitrogen concentration profile, which increases the dielectric constant and reduces trap density at the substrate interface
Implementation Method 3
a tailored nitrogen concentration profile, which increases the dielectric constant and reduces trap density at the substrate interface
Implementation Method 4
The positive VCG produces a field across the SONOS stack resulting in some negative charge at the conduction band energy level in the buried channel of silicon substrate channel to undergo Fowler-Nordheim tunneling (FNT) through the tunneling layer and into the charge trapping layer
Data Source
AI summary
A nonvolatile trapped-charge memory device and method of fabricating the same are described. Generally, the memory device includes a tunneling layer on a substrate, a charge trapping layer on the tunneling layer, and a blocking layer on the charge trapping layer. The tunneling layer includes a nitrided oxide film formed by annealling an oxide grown on the substrate using a nitrogen source. The tunneling layer comprises a first region proximate to the substrate, and a second region proximate to the charge trapping layer, and wherein the nitrogen concentration decreases from a first interface between the second region and the charge trapping layer to a second interface between the first region and the substrate to reduce nitrogen trap density at the second interface. Other embodiments are also described.