Nitrogen-Doped High-k Dielectric Gate Stack Process
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Solution Overview
Problem
Conventional poly-silicon gates in semiconductor devices face performance issues due to boron penetration and depletion effects, leading to increased equivalent thickness of the gate dielectric layer, reduced gate capacitance, and leakage current problems as transistors scale down, necessitating improved processes for high-k dielectric layers.
Innovation Solution
A semiconductor process involving sequential nitrogen-containing thermal treatments and annealing processes is performed on dielectric and barrier layers to dope ultra-light nitrogen atoms, improving the quality and reliability of high-k dielectric layers and reducing circuit leakage density and time-dependent dielectric breakdown in transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If poly-silicon is used as gate electrode to maintain device structure, then device fabrication is simplified, but boron penetration and depletion effects occur leading to increased equivalent thickness of gate dielectric layer and reduced gate capacitance
Solution Approach 1:
The patent changes the material parameter from poly-silicon to work function metals (such as titanium nitride, tantalum nitride) that are compatible with high-k dielectric layers. This material substitution eliminates boron penetration and depletion effects while maintaining the gate electrode function, thereby resolving the contradiction between manufacturing simplicity and electrical performance reliability.
Solution Approach 2:
The patent employs composite material structures combining high-k dielectric layers with work function metal layers. This composite approach allows the gate structure to simultaneously achieve high capacitance (through high-k material) and appropriate work function (through metal layer), eliminating the boron-related degradation issues of poly-silicon while maintaining fabrication feasibility.
2Length of moving object
If gate dielectric layer thickness is reduced to scale down transistor size, then transistor scaling is achieved, but breakdown voltage sustainability deteriorates causing serious leakage current
Solution Approach 1:
The patent fundamentally changes the dielectric parameter by transitioning from conventional low-k materials (SiO2) to high-k dielectric materials. This parameter change enables the use of thinner physical thickness while maintaining or enhancing the electrical insulation performance, thereby achieving transistor scaling without compromising breakdown voltage sustainability or inducing leakage current.
Solution Approach 2:
The patent applies high-k dielectric material specifically in the gate dielectric layer region where electrical performance is critical. This localized material optimization provides enhanced insulation properties exactly where needed, enabling thin gate structures to sustain breakdown voltage effectively while preventing leakage current in the scaled-down transistor.
3Device complexity
If conventional processes are used for high-k dielectric layer formation, then process simplicity is maintained, but quality and reliability of the dielectric layer are insufficient
Solution Approach 1:
The patent segments the dielectric layer formation process into multiple distinct steps: nucleation layer formation, high-k dielectric layer deposition, and interfacial layer formation. This segmentation allows each layer to be optimized independently with appropriate materials and processes, significantly improving the overall quality and reliability of the gate dielectric stack while maintaining reasonable process complexity through systematic organization.
Solution Approach 2:
The patent performs preliminary actions by forming nucleation layers and interfacial layers before depositing the main high-k dielectric layer. These preliminary layers prepare the substrate surface, improve adhesion, and prevent interfacial degradation, thereby enhancing the quality and reliability of the subsequent high-k dielectric layer while establishing a robust foundation for the gate stack.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The process enhances transistor performance by reducing equivalent oxide thickness, improving circuit leakage density, and increasing time-dependent dielectric breakdown reliability, addressing the limitations of conventional poly-silicon gates and high-k dielectric layers.
Implementation Method 1
performs a first nitrogen containing thermal treatment process on a dielectric layer to dope ultra-light nitrogen atoms into the dielectric layer
Implementation Method 2
a nitrogen containing gas annealing process with a processing temperature of 900° C. ̃1000° C. are sequentially performed on the barrier layer
Implementation Method 3
performs a second nitrogen containing thermal treatment process and then an annealing process (in-situ) on the barrier layer to dope nitrogen atoms into the barrier layer
Data Source
AI summary
A semiconductor process includes the following steps. A dielectric layer is formed on a substrate. A barrier layer is formed on the dielectric layer. An ammonia thermal treatment process with a processing temperature of 650° C.˜700° C. and a nitrogen containing gas annealing process with a processing temperature of 900° C.˜1000° C. are sequentially performed on the barrier layer. The present invention also provides a semiconductor process including the following steps. A dielectric layer is formed on a substrate. A first nitrogen containing thermal treatment process is performed on the dielectric layer. A barrier layer is formed on the dielectric layer. A second nitrogen containing thermal treatment process and then an annealing process are performed in-situ on the barrier layer.