Nitrogen-Doped Insulation Layer for Display Device Short Circuit Prevention
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Solution Overview
Problem
High-resolution display devices face challenges in pattern defects and short circuits due to the dense arrangement of lines in narrow spaces, leading to difficulties in photolithography processes and increased risk of pattern defects and short circuits between data metal lines on insulation layers.
Innovation Solution
A method involving the formation of a fifth auxiliary insulation layer with nitrogen-doped silicon nitride on a display device, using a blocking member as a mask to expose and polish specific areas, ensuring the upper surface of the main insulation layer is planarized and preventing excessive polishing, thereby minimizing short circuits and pattern defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithography process is performed on high-resolution display device with dense lines, then manufacturing complexity increases, but pattern defects occur more frequently
Solution Approach 1:
The patent divides the single photolithography process into multiple sequential processes: forming a first photosensitive film pattern, forming a second photosensitive film pattern, and then forming the final data metal line pattern. This segmentation allows each step to be optimized independently, reducing pattern defects while maintaining high manufacturing precision for dense line arrangements.
2Manufacturing precision
If data metal lines are arranged densely on insulation layer, then resolution increases, but short circuit risk increases
Solution Approach 1:
The patent introduces an intermediary insulation layer structure between data metal lines, specifically a second insulation layer formed between first and second data metal lines. This intermediary layer acts as a protective barrier that prevents short circuits while allowing the data metal lines to be arranged densely, thus maintaining high resolution without compromising reliability.
Solution Approach 2:
The patent performs preliminary formation of the second insulation layer and blocking members before forming the data metal line patterns. This preliminary action ensures that the insulation structure is already in place to prevent short circuits, allowing subsequent photolithography processes to focus on achieving high line density without worrying about short circuit risks.
3Manufacturing precision
If blocking member is used to prevent excessive polishing, then manufacturing precision improves, but device complexity increases
Solution Approach 1:
The blocking members are designed as temporary, disposable structures that are formed for a specific purpose (preventing excessive polishing during CMP), perform their function, and then removed. These blocking members are simple in structure and can be easily formed and removed, adding minimal complexity while providing precise control over the polishing process to maintain surface planarity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the easy patterning of data metal lines and reduces short circuits between data metal lines on the insulation layer, facilitating the manufacture of high-resolution display devices with improved reliability and efficiency.
Implementation Method 1
forming a fifth auxiliary insulation layer in a part of the fifth insulation layer by doping nitrogen ions in the fifth insulation layer and using the blocking member as a mask
Implementation Method 2
removing a portion of a fifth main insulation layer of the fifth insulation layer which does not overlap the fifth auxiliary insulation layer, by using a polishing device
Data Source
AI summary
A method of manufacturing a display device includes: forming an active layer on a substrate; forming a first insulation layer covering the active layer; forming a gate metal line on the first insulation layer; forming a third insulation layer covering the gate metal line and including a silicon oxide; forming a fourth insulation layer including a silicon nitride on the third insulation layer; forming a fifth insulation layer including a silicon oxide on the fourth insulation layer; arranging a blocking member over a region in which the active layer and the gate metal line overlap; forming a fifth auxiliary insulation layer by doping nitrogen ions in the fifth insulation layer; and exposing a part of an upper surface of the fourth insulation layer by removing a portion of a fifth main insulation layer of the fifth insulation layer which does not overlap the fifth auxiliary insulation layer.