Nitrogen-Doped Polysilicon Floating Gate for Flash Memory Reliability
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Solution Overview
Problem
Existing flash memory devices face issues with over programming and over erasing due to high conductivity at the interface between the floating gate and tunneling oxide layer, leading to reliability and durability problems, especially in miniaturized designs.
Innovation Solution
A non-volatile memory device is designed with a tunneling oxide layer, a floating gate comprising a first polysilicon layer with a specific grain size and a second polysilicon layer doped with nitrogen, along with a dielectric layer and a control gate, where nitrogen gas plasma treatment and high-temperature annealing improve the threshold voltage and prevent dopant diffusion, using a three-layer nitride structure to block outgassing and maintain stable electrical resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a doped polysilicon layer is used as the floating gate, then the conductivity is improved, but the grain size increases due to high-temperature processes, causing dopant gathering at the interface and leading to over programming and over erasing
Solution Approach 1:
The floating gate is divided into two separate polysilicon layers: a first doped polysilicon layer (with phosphorus or arsenic) and a second doped polysilicon layer (with nitrogen). This segmentation allows each layer to have different doping characteristics and grain size properties, preventing dopant gathering at the tunneling oxide interface while maintaining overall conductivity.
Solution Approach 2:
The floating gate uses a composite structure combining two differently doped polysilicon layers. The first layer provides base conductivity with phosphorus/arsenic doping, while the second layer with nitrogen doping prevents grain growth and dopant migration. This composite approach resolves the contradiction between needing high conductivity and maintaining grain size control.
2Reliability
If the grain size of the polysilicon layer is increased, then the conductivity is improved, but the dopant gathers at the interface with the tunneling oxide layer, causing over programming and over erasing
Solution Approach 1:
By segmenting the floating gate into two layers with different doping types, the patent prevents the harmful effect of dopant gathering. The nitrogen-doped second layer acts as a barrier that stops phosphorus/arsenic dopants from migrating to the tunneling oxide interface, even when grain size increases for conductivity improvement.
Solution Approach 2:
The second nitrogen-doped polysilicon layer serves as an intermediary barrier between the first doped polysilicon layer and the tunneling oxide. This intermediate layer prevents direct interaction between the phosphorus/arsenic dopants and the tunneling oxide interface, eliminating over programming and over erasing while allowing the first layer to maintain high conductivity through controlled grain growth.
3Volume of moving object
If miniaturization is implemented to meet product demand, then the device size is reduced, but the reliability and durability issues become more severe
Solution Approach 1:
The patent applies local quality by giving different regions of the floating gate different doping characteristics. The first layer has phosphorus/arsenic doping for conductivity, while the second layer has nitrogen doping specifically at the interface region to prevent dopant migration. This localized differentiation maintains reliability in miniaturized devices by preventing the interface problems that become more severe at smaller scales.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly reduces the occurrence of over programming and over erasing, enhancing the reliability and durability of the memory device by maintaining stable threshold voltage and electrical resistance, and improving product yield, especially in miniaturized designs.
Implementation Method 1
The grain size of the doped polysilicon layer is susceptible to subsequent high-temperature processes, thereby increased. However, when the size of the grain that is in contact with the tunneling oxide layer is larger, the dopant in the polysilicon layer becomes more likely to gather at the interface with the tunneling oxide layer.
Implementation Method 2
The floating gate includes a first polysilicon layer, a second polysilicon layer, and a nitrogen dopant. The second polysilicon layer includes a dopant and a plurality of second polysilicon grains having a second grain size. The nitrogen dopant is formed in the first polysilicon layer and in interstices between the plurality of first polysilicon grains.
Data Source
AI summary
A non-volatile memory device is provided. The non-volatile memory device includes a tunneling oxide layer, a floating gate, a dielectric layer, and a control gate. The tunneling oxide layer is formed on a substrate. The floating gate is formed on the tunneling oxide layer, and includes a first polysilicon layer, a second polysilicon layer, and a nitrogen dopant. A grain of the first polysilicon layer has a first grain size, and a grain of the second polysilicon layer has a second grain size that is greater than the first grain size. The nitrogen dopant is formed in interstices between the grains of the first polysilicon layer. The dielectric layer includes a first nitride film, an oxide layer, a nitride layer, and an oxide layer conformally formed on the floating gate. The control gate is formed on the dielectric layer.