Nitrogen-Graded EEPROM Floating Gate Insulator

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Solution Overview

Problem

Conventional EEPROM cells face charge leakage issues due to the thin thickness of the floating gate insulator, leading to poor charge retention, and the formation of N- and P-type doped regions during manufacturing can cause unwanted dopant diffusion into the substrate.

Innovation Solution

A method involving a semiconductor substrate with a thinned insulating layer and nitrogen incorporation closer to the surface, forming N- and P-type doped regions to enhance charge retention without dopant diffusion, using a nitrogen plasma and in situ doping to create a dual-gate MOS transistor with improved nitrogen distribution.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the floating gate insulator thickness is reduced to enable tunneling, then the tunneling efficiency is improved, but charge leakage increases

Engineering Contradiction:
Improvetunneling efficiencyVSAvoidcharge retention
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent applies local quality by creating distinct regions within the floating gate insulator with different nitrogen concentrations. The insulator has a first region closer to the tunnel window with lower nitrogen concentration to maintain tunneling efficiency, and a second region farther from the tunnel window with higher nitrogen concentration to prevent charge leakage. This spatial variation in composition allows simultaneous optimization of both tunneling and charge retention.

Inventive Principle:
Principle #3Local quality

2Reliability

If P-type dopants are implanted into the floating gate to create charge storage regions, then charge retention is improved, but dopant diffusion into the substrate occurs

Engineering Contradiction:
Improvecharge retentionVSAvoiddopant diffusion
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent uses nitrogen-incorporated oxide regions as intermediary structures to achieve charge storage without direct dopant implantation into the floating gate. The nitrogen-rich regions create potential wells that trap charges, replacing the need for P-type dopant regions. This intermediary approach eliminates dopant diffusion into the substrate while maintaining charge retention functionality.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent changes the physical and chemical parameters of the floating gate insulator by incorporating nitrogen at controlled concentrations and depths. Instead of using dopant concentration as the primary control parameter, the invention uses nitrogen concentration profile as the controlling parameter, creating a new mechanism for charge storage that avoids dopant diffusion issues.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method effectively reduces charge leakage and maintains charge retention in the floating gate while preventing dopant migration into the substrate, improving the overall performance of EEPROM cells.

Implementation Method 1

incorporating nitrogen at the level of the second surface, whereby the maximum nitrogen concentration is closer to the second surface than to the first surface

Methodology Applied
Scientific EffectPlasma: Plasma

Implementation Method 2

The tunnel window is thin enough to enable tunneling, of carriers between the floating gate and the underlying channel

Methodology Applied
Scientific EffectTunneling:

Implementation Method 3

The diffusion of dopant elements from the floating gate into the substrate can be observed during subsequent anneal steps

Methodology Applied
Scientific EffectDiffusion: Diffusion

Data Source

PatentUS8222094B2Method for manufacturing an EEPROM cell
Publication Date: 2012.07.17 STMICROELECTRONICS (ROUSSET) SAS
  • US8222094B2 patent drawing
  • US8222094B2 patent drawing
  • US8222094B2 patent drawing

AI summary

A method for manufacturing a cell of a non-volatile electrically erasable and programmable memory including a dual-gate MOS transistor. The method includes the steps of providing a semiconductor substrate covered with an insulating layer including a thinned down portion and having a first surface common with the substrate and a second surface opposite to the first surface; and incorporating nitrogen at the level of the second surface, whereby the maximum nitrogen concentration is closer to the second surface than to the first surface.