Nitrogen-Doped RFSOI Structure for Parasitic Coupling Suppression
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Solution Overview
Problem
High-frequency capacitive coupling between semiconductor devices and handle substrates in RFSOI structures leads to device cross-talk and signal losses, particularly above 1 GHz, due to parasitic surface conduction layers, which limits effective resistivity and affects signal fidelity.
Innovation Solution
A nitrogen-doped charge-trapping layer is implanted into the polysilicon material layer to suppress grain growth during anneal processes, reducing structural distortion and enhancing resistivity, thereby reducing capacitive coupling and improving signal fidelity by trapping free electrical charges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high resistivity semiconductor layer is used for the handle substrate to reduce capacitive coupling, then capacitive coupling is reduced, but device complexity increases
Solution Approach 1:
A charge-trapping layer is introduced as an intermediary between the handle substrate and the semiconductor material layer. This layer traps free electrical charges that would otherwise create parasitic surface conduction, effectively reducing capacitive coupling without requiring the entire handle substrate to have high resistivity. The charge-trapping layer acts as a mediator that decouples the electrical interaction while maintaining structural simplicity.
Solution Approach 2:
The patent changes the electrical parameters of the handle substrate by introducing a charge-trapping layer with specific trap density and depth characteristics. Instead of relying on bulk resistivity, the solution modifies the surface charge distribution parameters through controlled charge trapping, enabling capacitive coupling reduction while using standard resistivity substrates.
2Manufacturing precision
If nitrogen doping is applied to suppress grain growth during anneal, then structural distortion is reduced, but manufacturing complexity increases
Solution Approach 1:
Nitrogen doping is performed as a preliminary action before the anneal process to pre-condition the polysilicon charge-trapping layer. The nitrogen atoms are incorporated during deposition or through ion implantation prior to annealing, creating a compositionally modified layer that inherently resists grain growth during subsequent thermal processing. This preliminary modification eliminates the need for complex real-time control during annealing.
Solution Approach 2:
The chemical composition parameter of the charge-trapping layer is modified by incorporating nitrogen at controlled concentrations (e.g., 1-10 at%). This compositional change fundamentally alters the thermal behavior of the polysilicon, suppressing grain boundary mobility and preventing excessive grain growth during anneal, thereby maintaining fine-grained structure and reducing structural distortion.
3Reliability
If the charge-trapping layer traps free electrical charges to reduce capacitive coupling, then signal fidelity is improved, but device complexity increases
Solution Approach 1:
The charge-trapping layer serves as an intermediary that captures and holds free electrical charges, preventing them from creating parasitic conduction paths. By introducing this functional layer, the patent mediates the electrical interaction between the handle substrate and active devices, trapping charges that would otherwise degrade signal fidelity, while adding only a single thin functional layer rather than complex multi-layer structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The nitrogen-doped charge-trapping layer effectively reduces capacitive coupling, minimizes signal losses, and stabilizes the SOI substrate, allowing for improved lithographic patterning and high-frequency device performance with reduced warpage and enhanced signal fidelity.
Implementation Method 1
A nitrogen-doped charge-trapping layer is implanted into the polysilicon material layer to suppress grain growth during anneal processes, reducing structural distortion and enhancing resistivity, thereby reducing capacitive coupling and improving signal fidelity by trapping free electrical charges.
Implementation Method 2
A nitrogen-doped charge-trapping layer is implanted into the polysilicon material layer
Implementation Method 3
High-frequency capacitive coupling between semiconductor devices and handle substrates in RFSOI structures leads to device cross-talk and signal losses, particularly above 1 GHz, due to parasitic surface conduction layers
Data Source
AI summary
A semiconductor-on-insulator (SOI) substrate includes a handle substrate, a charge-trapping layer located over the handle substrate and including nitrogen-doped polysilicon, an insulating layer located over the charge-trapping layer, and a semiconductor material layer located over the insulating layer. The nitrogen atoms in the charge-trapping layer suppress grain growth during anneal processes used to form the SOI substrate and during subsequent high temperature processes used to form semiconductor devices on the semiconductor material layer. Reduction in grain growth reduces distortion of the SOI substrate, and facilitates overlay of lithographic patterns during fabrication of the semiconductor devices. The charge-trapping layer suppresses formation of a parasitic surface conduction layer, and reduces capacitive coupling of the semiconductor devices with the handle substrate during high frequency operation such as operations in gigahertz range.