Nitride Read-Only Memory Cell Threshold Voltage Control
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Solution Overview
Problem
As memory devices are scaled down, etching biases during the manufacturing process of nitride read-only memory cells lead to increased threshold voltage, higher working voltage, and increased power consumption, reducing the stability of the memory device.
Innovation Solution
The nitride layer in the ONO structure is deposited under specific gas flow ratios, reducing the threshold voltage of the nitride read-only memory cell without altering the existing manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the material of the spacer is changed from oxide to nitride to facilitate self-align contact etching, then the ease of manufacture is improved, but the threshold voltage of the cell increases
Solution Approach 1:
The patent changes the deposition parameters of the nitride layer, specifically using a nitrogen-rich deposition condition with a nitrogen flow rate of 30 sccm and silane flow rate of 10 sccm. This parameter change modifies the stoichiometry and electrical properties of the nitride layer, resulting in a lower threshold voltage (0.7V) compared to conventional deposition methods, thereby resolving the contradiction between ease of manufacture and threshold voltage stability
Solution Approach 2:
The patent creates a composite structure where the nitride layer is integrated within the ONO (oxide-nitride-oxide) stack. The nitride layer serves dual functions: as a trapping layer for charge storage and as a spacer material for self-align contact etching. The specific nitrogen-rich composition of this nitride layer provides both the structural function of a spacer and the electrical function of lowering threshold voltage, resolving the contradiction between manufacturing ease and device reliability
2Reliability
If the threshold voltage is increased by using nitride spacer material, then the working voltage of the memory device increases, but the power consumption increases and stability decreases
Solution Approach 1:
By changing the deposition parameters to create a nitrogen-rich nitride layer (N flow rate 30 sccm, SiH4 flow rate 10 sccm), the patent achieves a threshold voltage of 0.7V, which is lower than conventional nitride spacers. This reduced threshold voltage directly decreases the working voltage requirement and subsequently reduces power consumption, while maintaining the stability needed for reliable operation
3Reliability
If the threshold voltage is increased by using nitride spacer material, then the working voltage increases, but the damage to the bottom oxide intensifies
Solution Approach 1:
The nitrogen-rich deposition parameters (N flow rate 30 sccm, SiH4 flow rate 10 sccm) create a nitride layer with modified electrical characteristics that lower the threshold voltage to 0.7V. This reduced threshold voltage decreases the electric field stress during operation, thereby reducing the damage to the bottom oxide layer while maintaining adequate threshold voltage for device operation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively lowers the threshold voltage of the nitride read-only memory cell, maintaining stability and reducing power consumption while being compatible with existing manufacturing processes.
Implementation Method 1
a nitride layer is deposited on the first oxide layer via a first gas and a second gas
Data Source
AI summary
A nitride read-only memory cell and a method of manufacturing the same are provided. First, a substrate is provided, and a first oxide layer is formed on the substrate. Next, a nitride layer is deposited on the first oxide layer via a first gas and a second gas. The flow ratio of the first gas to the second gas is 2:1. After that, a second oxide layer is formed on the nitride layer. Then, a bit-line region is formed at the substrate. Afterward, a gate is formed on the second oxide layer. The first oxide layer, nitride layer, the second oxide layer and the gate compose a stack structure of the cell. Further, a spacer is formed on the side-wall of the stack structure.