NLDMOS Transistor P-Type Doped Region Carrier Insulation
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Solution Overview
Problem
The production cost of NLDMOS transistors with existing structures is high due to the need for deep P-type and N-type doped well regions to prevent carrier diffusion and interference between devices, which complicates the fabrication process and increases costs.
Innovation Solution
The introduction of a P-type doped reverse type region formed below the N-type drift region in the deep N-type well region, which physically connects with the P-type body regions, enhances carrier insulation without the need for deep P-type and N-type doped well regions, simplifying the fabrication process and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If deep P-type and N-type doped well regions are formed to prevent carrier diffusion and interference between devices, then carrier insulation performance is improved, but production cost and device complexity increase
Solution Approach 1:
The invention extracts and eliminates the deep P-type well and deep N-type well structures from the device architecture. Instead of forming these complex deep well regions, the patent uses a simplified structure where the N-type drift region directly contacts the P-type substrate, achieving carrier insulation through the inherent junction properties rather than complex deep well formations, thereby reducing fabrication process complexity while maintaining insulation performance
Solution Approach 2:
The invention inverts the conventional approach by not forming deep well regions to prevent carrier diffusion. Instead, it allows carriers to diffuse naturally and uses the resulting depletion layers and junction properties to achieve insulation. The P-type ion implanting region is formed after the N-type drift region, reversing the conventional doping sequence and achieving insulation through the interaction of these regions rather than through deep well containment
2Reliability
If deep P-type and N-type doped well regions are formed to prevent carrier diffusion, then carrier insulation performance is improved, but production cost increases
Solution Approach 1:
The invention removes the expensive deep well formation processes from the fabrication sequence. By eliminating the need to form deep P-type and N-type well regions through complex ion implantation and annealing steps, the patent significantly reduces production cost while achieving the same carrier insulation function through simpler junction-based mechanisms
Solution Approach 2:
The invention replaces expensive, complex deep well structures with simpler, more cost-effective doping regions that achieve the same functional outcome. The P-type ion implanting region and N-type drift region interaction provides the necessary carrier insulation without requiring costly deep well formation processes, making the device more economically viable
3Reliability
If deep P-type and N-type doped well regions are formed sequentially, then carrier diffusion prevention is achieved, but manufacturing time and process steps increase
Solution Approach 1:
The invention extracts and eliminates the sequential deep well formation steps from the fabrication process. By removing the need to form deep P-type well followed by deep N-type well in sequence, the patent reduces the number of fabrication steps and increases productivity, achieving carrier diffusion prevention through the interaction of the P-type ion implanting region and N-type drift region instead
Solution Approach 2:
The invention performs preliminary doping actions to create regions that will interact to prevent carrier diffusion. The P-type ion implanting region is formed with characteristics that anticipate its interaction with the subsequent N-type drift region, enabling carrier diffusion prevention through their combined effect rather than through sequential deep well containment, thereby streamlining the manufacturing process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents carrier interference between devices, reduces production costs by eliminating the need for deep well regions, and maintains the performance of NLDMOS transistors by forming depletion layers that prevent carrier escape and external interference.
Implementation Method 1
forming depletion layers that prevent carrier escape and external interference
Data Source
AI summary
An N-type Lateral Diffused Metal-Oxide-Semiconductor (NLDMOS) transistor is provided. The NLDMOS transistor comprises a P-type substrate; and a semiconductor layer having a deep N-type well region formed on the P-type substrate. Further, the NLDMOS transistor also includes at least a P-type body region and an N-type drift region formed in the deep N-type well region; and an N-type heavily doped drain region formed in the N-type drift region. Further, the NLDMOS transistor includes a P-type doped reverse type region formed below the N-type drift region in the deep N-type well region, being physically connected with the first P-type body region, and preventing carriers from escaping between the N-type source region and external devices.