NMI Disable Control for Exception Handler Return

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Solution Overview

Problem

In computer systems, the premature re-enablement of nonmaskable interrupts (NMIs) upon returning from exceptions can lead to nested NMI execution, causing operating system instability and potential fatal errors, especially in high-reliability environments where NMIs and exceptions coexist.

Innovation Solution

A nested NMI prevention unit is implemented to prevent premature enabling of NMIs by temporarily disabling further NMIs during exception handling, using an NMI disable control to determine if an exception occurred within an NMI handler and preserving this indication to conditionally re-enable NMI delivery upon exception handler return.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the processor re-enables NMIs upon returning from exceptions, then NMI delivery is restored, but nested NMI execution may occur causing system instability

Engineering Contradiction:
Improvesystem stabilityVSAvoidnested NMI execution
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent introduces an intermediary mechanism (NMI disable control and nested NMI prevention unit) that mediates between exception handler return and NMI re-enablement. This intermediary tracks whether an exception occurred during NMI handling and conditionally prevents NMI re-enablement, thereby resolving the contradiction between restoring NMI delivery and preventing nested NMI execution.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent implements a feedback mechanism where the nested NMI prevention unit monitors the state of the NMI disable control and the exception handler execution context. Based on this feedback, the system dynamically determines whether to re-enable NMIs, preventing nested execution while maintaining system reliability.

Inventive Principle:
Principle #23Feedback

2Object-affected harmful factors

If NMIs are continuously disabled during exception handling, then nested NMI execution is prevented, but legitimate NMI delivery is delayed

Engineering Contradiction:
Improvenested NMI executionVSAvoidNMI delivery delay
Core Design Contradiction:
Object-affected harmful factorsVSLoss of time

Solution Approach 1:

The patent applies dynamics by making the NMI disable state conditional rather than static. The NMI disable control is activated only when an exception occurs during NMI handling, and is deactivated when the exception handler returns without indicating an exception. This dynamic approach prevents nested NMIs only when necessary, minimizing delivery delays for legitimate NMIs.

Inventive Principle:
Principle #15Dynamics

3Productivity

If the processor uses a simple return mechanism from exceptions, then handling is fast, but NMI re-enablement cannot be conditionally controlled

Engineering Contradiction:
Improveexception handling speedVSAvoidNMI control mechanism
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent merges the exception return mechanism with the NMI control mechanism. The exception handler return instruction simultaneously performs the return operation and updates the NMI disable control based on whether an exception occurred during handling. This merging maintains fast exception handling while enabling conditional NMI re-enablement without significantly increasing complexity.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentEP3198402B1Avoiding premature enabling of nonmaskable interrupts when returning from exceptions
Publication Date: 2021.06.30 INTEL CORP
  • EP3198402B1 patent drawingFigure 1
  • EP3198402B1 patent drawingFigure 2
  • EP3198402B1 patent drawingFigure 3

AI summary

A processor of an aspect includes a decode unit to decode an exception handler return instruction. The processor also includes an exception handler return execution unit coupled with the decode unit. The exception handler return execution unit, responsive to the exception handler return instruction, is to not configure the processor to enable delivery of a subsequently received nonmaskable interrupt (NMI) to an NMI handler if an exception, which corresponds to the exception handler return instruction, was taken within the NMI handler. The exception handler return execution unit, responsive to the exception handler return instruction, is to configure the processor to enable the delivery of the subsequently received NMI to the NMI handler if the exception was not taken within the NMI handler. Other processors, methods, systems, and instructions are disclosed.