NMONITOR NWAIT NPOLL Instructions for Multi-Address Memory Monitoring

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Solution Overview

Problem

Existing hardware struggles to effectively exploit fine-grained parallelism due to high overhead in scheduling tasks and switching between them, limiting the efficiency of monitoring multiple addresses for write-to-memory activities.

Innovation Solution

Introduction of new instructions, NMONITOR, NWAIT, and NPOLL, which allow software to monitor multiple non-contiguous addresses and enter an optimized state until a write operation occurs, reducing power consumption and overhead by asynchronously notifying software of write events.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If active polling mechanism is used to monitor multiple addresses, then software can detect write events, but power consumption and overhead increase significantly

Engineering Contradiction:

Improvewrite event detectionVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The processor enters periodic low-power states (hlt/wait states) between monitoring intervals, only becoming active when a write event occurs to the monitored address. This transforms continuous active polling into periodic monitoring with intervals of low-power states, significantly reducing power consumption while maintaining reliable event detection.

Inventive Principle:

Principle #19Periodic action

Solution Approach 2:

The monitoring mechanism uses hardware-supported events that automatically wake the processor from low-power states when monitored addresses are written to. The system serves itself by having the hardware detect write events and trigger processor wake-up, eliminating the need for continuous software polling and reducing overall system overhead.

Inventive Principle:

Principle #25Self-service

2Reliability

If active polling is implemented to monitor multiple addresses, then write events can be detected, but scheduling overhead increases

Engineering Contradiction:

Improvewrite event detectionVSAvoidscheduling overhead

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent replaces the mechanical software polling loop with a hardware-supported event monitoring system. The processor's monitoring hardware automatically tracks writes to multiple addresses and generates events, substituting the manual software polling mechanism with an automated hardware-based system that reduces scheduling complexity.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The monitoring mechanism introduces an intermediary event system between the monitored addresses and the software. Instead of software directly polling addresses, the hardware monitoring layer acts as an intermediary that detects writes and generates events, simplifying the software's interaction and reducing its scheduling overhead.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Use of energy by moving object

If MONITOR/MWAIT instructions monitor a single address range, then power efficiency is improved, but the ability to monitor multiple non-contiguous addresses is limited

Engineering Contradiction:

Improvepower efficiencyVSAvoidnumber of monitorable addresses

Core Design Contradiction:

Use of energy by moving objectVSAdaptability or versatility

Solution Approach 1:

The patent extends the MONITOR/MWAIT mechanism to support multiple non-contiguous address ranges through a set of related instructions (NMONITOR, NWAIT, NPOLL). This universal monitoring system can handle any number of address ranges, making the power-efficient monitoring capability applicable to diverse scenarios requiring monitoring of multiple scattered addresses rather than just a single contiguous range.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The monitoring capability is segmented into multiple independent address range monitors, each capable of being monitored separately. Instead of requiring a single large contiguous address range, the system divides monitoring into multiple smaller address segments, allowing flexible monitoring of scattered memory locations while maintaining power efficiency through selective event-driven wake-up.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS10394678B2Wait and poll instructions for monitoring a plurality of addresses

Publication Date: 2019.08.27 INTEL CORP

AI summary

A processor core includes a decode circuit to decode an instruction. The processor core further includes a monitor circuit, where the monitor circuit includes a data structure to store a plurality of entries for addresses that are being monitored by the monitor circuit and a triggered queue to store a plurality of addresses for which a triggering event occurred. The processor core further includes an execution circuit to execute the decoded instruction to dequeue an address from the triggered queue and return the dequeued address in response to a determination that the triggered queue is not empty.