NMOS Channel Strain via Dislocation-Induced Stress
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Solution Overview
Problem
Current microelectronic devices with NMOS/PMOS transistor structures face limitations in optimizing stress, which hampers performance, particularly in electron mobility and drive performance.
Innovation Solution
The method involves forming a dislocation in the source/drain region of the NMOS portion of a substrate, inducing strain in the channel region by using a stress material with a dual layer stack, such as silicon dioxide and silicon nitride, to enhance electron mobility without introducing dislocations in the PMOS portion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If stress is introduced into the channel region to improve electron mobility, then device drive performance is improved, but dislocations may be introduced that degrade device reliability
Solution Approach 1:
The patent applies local quality by creating dislocations specifically in the NMOS channel region while avoiding the PMOS region. This is achieved through selective processing steps that induce stress and dislocations only where needed for electron mobility enhancement, leaving the PMOS devices unaffected and maintaining their reliability.
Solution Approach 2:
The patent segments the substrate into NMOS and PMOS portions and applies different stress engineering treatments to each. The NMOS portion receives dislocation-induced stress for improved electron mobility, while the PMOS portion maintains its original structure, allowing independent optimization of each device type.
2Productivity
If stress engineering is applied to both NMOS and PMOS devices, then both device types benefit, but the complexity of the processing increases
Solution Approach 1:
The patent uses local quality to apply stress engineering selectively only to the NMOS portion of the substrate. By identifying that electron mobility enhancement is primarily needed for NMOS devices, the processing complexity is reduced compared to applying identical stress engineering to both NMOS and PMOS devices.
3Speed
If dislocations are introduced in the source/drain region, then strain is induced in the channel region improving mobility, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies preliminary action by forming the dislocations in the source/drain region before final device fabrication steps. This preliminary dislocation formation allows subsequent processing steps to work with the pre-established strain field, reducing the precision requirements for later manufacturing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly improves electron mobility and drive performance of NMOS devices by creating a dislocation-induced strain in the channel region, while maintaining PMOS performance, thus optimizing stress engineering for better microelectronic device performance.
Implementation Method 1
inducing strain in the channel region by using a stress material with a dual layer stack
Data Source
AI summary
Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a source/drain region in an NMOS portion of a substrate, wherein the source/drain region of the NMOS portion comprises at least one dislocation, and wherein a PMOS source/drain region in a PMOS portion of the substrate does not comprise a dislocation.