NMOS Negative Charge Pump With Bootstrap Gating for Low-Impedance Output
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Solution Overview
Problem
Existing negative charge pump circuits face inefficiencies in generating high-magnitude negative voltages due to weakening p-channel MOS transistors, voltage drops, and high output impedance, which restricts current driving capability and requires complex clocking schemes.
Innovation Solution
A charge pump circuit design utilizing n-channel MOS transistors with boost and bootstrap capacitors driven by clock signals with different duty cycles, allowing for efficient generation of negative voltages with lower output impedance and improved current driving capability, while using low-voltage transistors to reduce power consumption and circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If multiple charge pump stages are coupled in series to generate higher magnitude negative voltage, then the output voltage magnitude increases, but the p-channel MOS transistors become weaker and voltage conversion efficiency reduces
Solution Approach 1:
The patent inverts the conventional charge pump architecture by using n-channel MOS transistors instead of p-channel MOS transistors as the primary switching devices. This inversion allows the use of low-voltage transistors that can operate efficiently at lower supply voltages, maintaining strong transistor operation even in cascaded stages and thereby preserving voltage conversion efficiency while achieving higher output voltage magnitudes.
Solution Approach 2:
The patent changes the key parameter of transistor type from p-channel to n-channel, and introduces bootstrap capacitors to dynamically adjust the gate-source voltage of the n-channel transistors. This parameter change enables the transistors to maintain optimal operating conditions throughout the charge pump stages, preventing degradation of voltage conversion efficiency as more stages are added.
2Strength
If multiple charge pump stages are coupled in series to generate higher magnitude negative voltage, then the output voltage magnitude increases, but the bulk to source/drain voltage increases which can result in breakdown
Solution Approach 1:
The patent introduces bootstrap capacitors as intermediary elements that couple the gate of each n-channel transistor to the previous stage's output. These capacitors act as mediators that dynamically boost the gate voltage to maintain appropriate bulk-to-source and bulk-to-drain voltage differences, preventing transistor breakdown even when generating high magnitude negative voltages through cascaded stages.
3Device complexity
If diode-connected transistors are used in charge pump stages, then the circuit structure is simplified, but voltage drop occurs and voltage efficiency becomes poor
Solution Approach 1:
The patent extracts the diode connection constraint from the transistor configuration. Instead of using diode-connected transistors where the gate is shorted to the drain, the patent uses properly gated n-channel transistors with bootstrap capacitors that provide the necessary voltage boosting without the voltage drop penalties of diode connections. This extraction of the diode connection requirement maintains structural simplicity while eliminating the associated voltage efficiency losses.
4Use of energy by moving object
If low-voltage transistors are used to reduce power consumption and circuit area, then power consumption and area are reduced, but the ability to generate high voltages is limited
Solution Approach 1:
The patent employs periodic clock signals to drive the charge pump stages, with bootstrap capacitors charged and discharged in periodic cycles. This periodic action allows low-voltage transistors to accumulate voltage boosting effects over multiple cycles, enabling them to generate high output voltages despite their low supply voltage operation, thereby maintaining low power consumption while achieving high voltage generation capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The circuit achieves efficient generation of high-magnitude negative voltages with reduced voltage drops and improved current driving capability, maintaining performance with smaller circuit area and simpler clocking, addressing the limitations of prior art solutions.
Implementation Method 1
a first boost capacitor having a first plate coupled to the first node and a second plate coupled to receive a first clock signal
Implementation Method 2
a first bootstrap capacitor having a first plate coupled to the first control terminal and a second plate coupled to receive a second clock signal
Data Source
AI summary
A charge pump circuit includes a boost capacitor driven by a first clock signal and a bootstrap capacitor driven by a second clock signal. The first and second clock signals have different duty cycles, with the duty cycle of the second clock signal being smaller than the duty cycle of the first clock signal. An input transistor is coupled between an input node and a boost node coupled to the boost capacitor. The control terminal of the input transistor is coupled to the bootstrap capacitor. A bootstrap transistor coupled between the boost node and the control terminal of the input transistor is driven by a logical inverse of the first clock signal.