NMOS Comparator Input Circuit for NBTI-Stable Wide Voltage Range
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Solution Overview
Problem
The PMOS transistors in rail-to-rail type input circuits of comparators are prone to negative-bias temperature instability (NBTI) degradation, leading to imbalance in differential pairs and reduced detection accuracy, especially when receiving a DC reference signal with a low voltage level.
Innovation Solution
Incorporating a differential pair circuit with NMOS transistors and using level shift circuits to raise the voltage of input signals when they fall below a predetermined threshold, minimizing NBTI degradation and maintaining operability across a wide input voltage range while reducing circuit size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a rail-to-rail type input circuit using PMOS transistors is used to achieve wide input voltage range, then the input voltage range is extended, but NBTI degradation occurs leading to differential pair imbalance and reduced detection accuracy
Solution Approach 1:
The patent changes the transistor type parameter from PMOS to NMOS in the differential pair circuit. NMOS transistors are used instead of PMOS transistors, which eliminates NBTI degradation while maintaining the ability to handle wide input voltage ranges through appropriate circuit design and level shifting mechanisms.
Solution Approach 2:
The patent introduces level shift circuits as intermediary components between the input signals and the NMOS differential pair circuit. These level shift circuits adjust the voltage levels of input signals to match the operating range of the NMOS differential pair, enabling wide input voltage range acceptance while maintaining accurate differential comparison.
2Adaptability or versatility
If PMOS transistors are used in the differential pair circuit to handle low voltage level DC reference signals, then the input circuit can accept low voltage signals, but NBTI degradation increases causing differential pair imbalance
Solution Approach 1:
The patent changes the transistor type parameter from PMOS to NMOS in the differential pair circuit. NMOS transistors are used instead of PMOS transistors, which eliminates NBTI degradation while maintaining the ability to handle wide input voltage ranges through appropriate circuit design and level shifting mechanisms.
3Measurement precision
If NMOS differential pair circuit is used to avoid NBTI degradation, then detection accuracy is maintained, but the circuit cannot handle wide input voltage range from power supply voltage to ground voltage
Solution Approach 1:
The patent introduces level shift circuits as intermediary components between the input signals and the NMOS differential pair circuit. These level shift circuits adjust the voltage levels of input signals to match the operating range of the NMOS differential pair, enabling wide input voltage range acceptance while maintaining accurate differential comparison.
Solution Approach 2:
The patent designs the input circuit with multi-functional capabilities: the NMOS differential pair circuit handles the core comparison function with high accuracy, while level shift circuits extend the input voltage range acceptance. This universal design allows the circuit to maintain detection accuracy across wide input voltage ranges from power supply voltage to ground voltage.
Data Source
AI summary
A comparator includes a differential pair circuit comprising NMOS transistors, the differential pair circuit configured to output a signal corresponding to a difference between first and second input signals supplied thereto, and an input circuit configured to raise a voltage level of the first input signal supplied to the differential pair circuit when the voltage of the first input signal is less than a predetermined threshold value.