NMOS Current Sink With Negative Voltage Blocking for Gate Pull-Down

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Solution Overview

Problem

Current current sink circuits fail to provide a strong gate pull-down current with low quiescent current and negative voltage tolerance, especially in harsh automotive environments with fast battery transients and voltage levels of 40V to -25V, leading to potential inadvertent actuator activation.

Innovation Solution

A current sink circuit design using multiple NMOS transistors in series with a negative voltage blocking circuit, coupled with a control signal generation circuit and pull-down current limiting circuit, which draws voltage from NMOS power FET drains and protects against high and low transient voltages, ensuring the gate control node is properly pulled down without drawing current when the ignition is ON.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a strong gate pull down current is provided to ensure the actuator remains OFF, then reliability is improved, but quiescent current increases

Engineering Contradiction:
Improveactuator OFF condition assuranceVSAvoidquiescent current
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The pull-down circuit is designed to be dynamically controllable through the ignition signal. When ignition is ON, the circuit provides strong pull-down current to ensure reliability. When ignition is OFF, the circuit reduces its activity to minimize quiescent current consumption. This dynamic behavior is achieved through the ignition signal controlling the activation state of the pull-down transistors.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The circuit changes its operational parameters based on the ignition signal state. The pull-down current strength is adjusted according to whether the ignition is ON or OFF. This parameter change allows the circuit to provide strong pull-down current when needed for reliability while reducing current consumption during normal operation to maintain low quiescent current.

Inventive Principle:
Principle #35Parameter changes

2Adaptability or versatility

If the circuit operates in harsh automotive environments with voltage transients up to 40V and -25V, then adaptability is improved, but circuit protection becomes more complex

Engineering Contradiction:
Improvevoltage transient toleranceVSAvoidprotection circuit complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The circuit incorporates protection mechanisms that are prepared in advance to handle voltage transients. The protection circuitry is designed to anticipate and cushion against the harsh automotive voltage environment, including transients up to 40V and -25V. This beforehand cushioning approach allows the circuit to operate reliably in harsh conditions without requiring complex real-time response mechanisms.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Solution Approach 2:

The circuit uses intermediary protection elements that mediate between the harsh external voltage environment and the sensitive internal circuitry. These intermediary components buffer the impact of voltage transients, allowing the core circuit to operate in harsh automotive environments without direct exposure to extreme voltage conditions, thereby managing protection complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If the pull down current is active under any phase of operation, then reliability is improved, but quiescent current increases

Engineering Contradiction:
Improvecontinuous pull down capabilityVSAvoidoverall quiescent current
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The pull-down current is activated periodically or conditionally based on operational phases rather than continuously. The ignition signal controls the activation of the pull-down circuit, enabling it to be active during critical phases (when ignition is ON) and inactive during non-critical phases. This periodic action maintains reliability during operation while reducing overall quiescent current consumption.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The circuit applies partial pull-down action rather than full continuous pull-down. The ignition signal modulates the pull-down current strength, providing sufficient pull-down capability during operational phases when reliability is critical, while reducing or disabling the pull-down current during non-operational phases to minimize quiescent current. This partial action approach balances reliability requirements with energy efficiency.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentEP3656057B1Current sink with negative voltage tolerance
Publication Date: 2023.12.13 TEXAS INSTRUMENTS INC
  • EP3656057B1 patent drawingFigure 1~2
  • EP3656057B1 patent drawingFigure 3~6
  • EP3656057B1 patent drawingFigure 4

AI summary

A current sink circuit is coupled to pull down a gate control node (GCN) (402) for an NMOS power FET (422) that controls an actuator (424). The current sink circuit includes first and second NMOS transistors (MNO, MN2) coupled in series between the GCN (402) and a lower rail. The first NMOS transistor (MNO) has a gate and drain coupled together through a resistor (RGSN). The current sink circuit also includes a control signal generation circuit (CSGC) (404) and a negative voltage blocking circuit (406). The CSGC (404) is coupled to receive at least one voltage input (e.g., any of DRN1, DRN2, DRN3, REGULATOR) and an ignition signal (IGNITION) and to provide a first control signal (CSl) and a second control signal (CS2). The negative voltage blocking circuit (406) is coupled to pass the first control signal from the CSGC (404) to the gate of the first NMOS transistor (MNO) and to block a negative voltage on the GCN (402) from reaching the CSGC (404). The second control signal (CS2) is coupled to the gate of the second NMOS transistor (MN2).