NMOS EEPROM P-well Segmentation for Voltage Stress Reduction
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Solution Overview
Problem
N-channel EEPROM devices face challenges in minimizing bit disturbances and voltage withstand requirements during programming and erasing, with existing technologies requiring high voltages that stress smaller geometry circuit elements and necessitating byte select transistors for partial row operations, leading to inefficiencies and increased silicon area overhead.
Innovation Solution
The solution involves creating independently programmable memory segments within the EEPROM array by fabricating multiple P-wells within a deep N-well or segmenting a P-well using p-n junction or dielectric isolation, allowing for reduced voltage stress and eliminating the need for byte select transistors through biased cell elements and circuitry during write and erase operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high voltage is applied during programming and erasing operations, then the programming and erasing functions are achieved, but voltage breakdown occurs in smaller geometry circuit elements
Solution Approach 1:
The memory array is divided into multiple independently programmable segments through P-well segmentation. Each segment can be programmed or erased independently, allowing voltage to be applied only to selected segments rather than the entire array. This segmentation reduces the voltage stress on any single circuit element while maintaining the required programming and erasing functions.
Solution Approach 2:
Different voltage levels are applied to different regions of the memory array based on operational requirements. During programming or erasing operations, high voltage is applied only to the selected segment and its associated control lines, while other regions operate at lower voltages. This localized voltage application minimizes overall voltage stress on the circuit elements.
2Adaptability or versatility
If byte select transistors are added to enable partial row operations, then byte-level selectability is achieved, but silicon area overhead increases
Solution Approach 1:
The memory array is segmented into independently programmable regions using P-well structures. Each segment can be independently selected and programmed or erased without requiring additional byte select transistors. This segmentation provides byte-level selectability at the well level rather than requiring transistor-level control, thereby reducing silicon area overhead while maintaining adaptability.
Solution Approach 2:
The byte select transistor functionality is extracted and replaced by P-well segmentation control. Instead of using transistors to select bytes, the invention uses the P-well structure itself to define independently programmable segments. This eliminates the need for byte select transistors and their associated control circuitry, reducing area overhead while preserving byte-level selectability.
3Device complexity
If the entire row is programmed during erase operations (as in Caywood approach), then row select transistor elimination is achieved, but programming efficiency decreases
Solution Approach 1:
The memory array is divided into multiple independently programmable segments through P-well segmentation. This allows selective programming or erasing of only the required segments rather than the entire row. The segmentation is achieved through physical separation of P-wells, which naturally isolates the electrical characteristics of each segment. This enables partial row operations without requiring additional byte select transistors, maintaining low device complexity while improving programming efficiency.
Solution Approach 2:
The invention enables dynamic selection of memory segments for programming or erasing operations. By controlling the voltage applied to different P-well segments, the system can dynamically select which segments to operate on, allowing flexible and efficient partial row operations. This dynamic control is achieved through the inherent electrical isolation of segmented P-wells combined with selective voltage application.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes bit disturbances and voltage requirements, enhances endurance by allowing selective programming of memory segments, and reduces silicon area overhead, thereby improving the reliability and efficiency of EEPROM devices.
Implementation Method 1
a method for programming and erasing an array of NMOS eeprom cells that minimizes bit disturbances and voltage withstand requirements
Data Source
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AI summary
A method for programming and erasing an array of NMOS electrically erasable programmable read only memory (EEPROM) cells that minimizes bit disturbances and high voltage requirements for the memory array cells and supporting circuits. In addition, the array of N-channel memory cells may be separated into independently programmable memory segments by creating multiple, electrically isolated P-wells upon which the memory segments are fabricated. The multiple, electrically isolated P-wells may be created, for example, by p-n junction isolation or dielectric isolation.