NMOS ESD Protection Circuit Using Parasitic BJT Discharge
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Solution Overview
Problem
Semiconductor memories are vulnerable to Electro-Static Discharge (ESD) damage due to the continuous reduction in size, which can cause high voltage and current, leading to circuit damage.
Innovation Solution
An ESD protection circuit is designed with a p-type substrate, a p-type well, and two NMOS transistors with a common active region, along with a LDD region near the source of one transistor, to effectively discharge ESD current through parasitic BJT activation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor memory size is continuously reduced, then integration density is improved, but ESD vulnerability increases
Solution Approach 1:
The ESD protection circuit is segmented into multiple functional regions: a first protection region with a first ESD protection circuit connected to the first power supply terminal, and a second protection region with a second ESD protection circuit connected to the second power supply terminal. This segmentation allows each region to independently protect against ESD events, providing targeted protection while maintaining high integration density in the reduced-size memory device.
2Reliability
If ESD protection circuit is added to protect memory, then ESD robustness is improved, but device complexity increases
Solution Approach 1:
The ESD protection circuits are merged with the power supply terminals of the memory device. The first ESD protection circuit is integrated into the first power supply terminal, and the second ESD protection circuit is integrated into the second power supply terminal. This merging approach provides comprehensive ESD protection without adding separate complex protection structures, thereby maintaining relatively simple device architecture while improving ESD robustness.
3Reliability
If multiple ESD protection circuits are used for different power supplies, then ESD protection coverage is improved, but manufacturing complexity increases
Solution Approach 1:
The ESD protection circuits are designed with multi-functionality to handle different power supply scenarios. Each ESD protection circuit can operate independently with its associated power supply terminal, providing universal protection coverage. This universal design approach simplifies manufacturing by using standardized protection circuit blocks that can be consistently fabricated across different memory device configurations and power supply arrangements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the ESD protection capability by creating a common active region for the NMOS transistors and utilizing parasitic BJT to discharge ESD current, while also reducing leakage current and power consumption.
Implementation Method 1
the parasitic BJT can be triggered to be turned on through the substrate in the ESD protection circuit, so that the ESD current can be discharged through the parasitic BJT
Implementation Method 2
The Electro-Static Discharge (ESD) in different degrees will occur in the manufacturing process of semiconductor memories and in the final system applications
Data Source
Figure 1~2
Figure 3~4(b)
Figure 5(a)~6(d)
AI summary
Embodiments of the present disclosure provide an Electro-Static Discharge (ESD) protection circuit, an ESD protection method, a semiconductor memory and an ESD protection system. The ESD protection circuit includes a p-type substrate; a p-type well formed on the p-type substrate; a first Negative channel Metal Oxide Semiconductor (NMOS) transistor and a second NMOS transistor formed in the p-type well, where a drain of the first NMOS transistor is connected to a source of the second NMOS transistor; and a Lightly Doped Drain (LDD) region formed in proximity to a source of the first NMOS transistor.