NMOS ESD Clamp Circuit With Diode Trigger Voltage Control
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Solution Overview
Problem
Existing ESD protection devices like SCRs and GGNMOS face challenges in low-voltage operations and thermal vulnerability, respectively, while GCMOS is difficult to manufacture and control, necessitating improved ESD protection circuits for semiconductor circuits.
Innovation Solution
An ESD protection circuit with an NMOS transistor, RC circuit, clamping circuit, and a gate-coupled PMOS switch is designed, where the number of diodes in the clamping circuit is controlled based on the breakdown and operating voltage of the internal circuit, and a switch is used to selectively activate the clamping circuit during normal operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of diodes in the clamping circuit is increased to raise the trigger voltage above the operating voltage, then the ESD protection circuit can prevent circuit malfunction, but the trigger voltage may exceed the breakdown voltage and cause circuit destruction
Solution Approach 1:
The patent employs a dynamic switching mechanism using a PMOS transistor controlled by an RC circuit that responds to voltage changes. When voltage exceeds a threshold, the PMOS switches to connect or disconnect the clamping circuit, dynamically adjusting the trigger voltage rather than using a fixed number of diodes. This resolves the contradiction by making the protection level adaptive rather than static.
Solution Approach 2:
The patent changes the parameter of trigger voltage dynamically through the switching action of the PMOS transistor. The RC circuit detects voltage changes and controls the PMOS gate, thereby changing the effective number of diodes in the clamping circuit based on the detected voltage level. This allows the system to adapt the trigger voltage parameter to different operating conditions.
2Reliability
If SCR is used for ESD protection due to high current driving capability, then excellent tolerance characteristics are achieved, but unwanted turn-on occurs in low-voltage operations
Solution Approach 1:
The patent applies local quality by using different device characteristics in different parts of the circuit. The PMOS transistor provides high current driving capability where needed for ESD protection, while the RC circuit and voltage threshold mechanism provide stability in low-voltage operation regions. This localized application of different properties resolves the contradiction between current capability and operational stability.
3Ease of manufacture
If GGNMOS is used for ESD protection due to ease of manufacture, then control simplicity is achieved, but thermal deterioration vulnerability increases
Solution Approach 1:
The patent creates a composite protection circuit combining GGNMOS simplicity with additional protective elements. The RC circuit and PMOS transistor are added to the basic GGNMOS structure to create a composite system that maintains manufacturing ease while adding thermal stability through the voltage-triggered switching mechanism that prevents continuous operation under thermal stress.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively controls the trigger voltage of the NMOS transistor within the operating and breakdown voltage ranges, preventing circuit malfunction and degradation by ensuring the ESD protection circuit operates efficiently during both ESD events and normal conditions.
Implementation Method 1
a resistor-capacitor (RC) circuit connected in parallel with the NMOS transistor and including a capacitor and a resistor
Implementation Method 2
a resistor-capacitor (RC) circuit connected in parallel with the NMOS transistor and including a capacitor and a resistor
Implementation Method 3
a clamping circuit connected in parallel with the resistor of the RC circuit and including a plurality of diodes; and a switch connecting the clamping circuit to a gate node of the NMOS transistor, wherein a number of the plurality of diodes is determined based on a breakdown voltage
Data Source
AI summary
An electrostatic discharge protection circuit includes an NMOS transistor connected to a supply voltage pin through a first node and connected to a ground pin through a second node, an RC circuit connected in parallel with the NMOS transistor and including a capacitor and a resistor, and a clamping circuit connected in parallel with the resistor of the RC circuit and including a plurality of diodes; and a switch connecting the clamping circuit to a gate node of the NMOS transistor, wherein a number of the plurality of diodes is set based on a breakdown voltage and an operating voltage of an internal circuit to be protected by the ESD protection circuit, and the switch includes a PMOS transistor connecting the gate node of the NMOS transistor to the clamping circuit and a sub-RC circuit connected in parallel with the PMOS transistor and including a sub-capacitor and a sub-resistor.