NMOS Transistor ESD Protection via PP Region Placement

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Solution Overview

Problem

Conventional n-type metal oxide semiconductor (NMOS) transistors for electrostatic discharge (ESD) require additional fabrication procedures and implants, which increase complexity and cost, and do not effectively manage trigger and holding voltages during ESD events.

Innovation Solution

The design of an NMOS transistor without implants, featuring a first and second n-type plus (NP) region, a first and second p-type plus (PP) region, shallow trench isolation (STI) region, and a gate stack, where the first PP region is strategically positioned between the NP regions to reduce trigger voltage and increase holding voltage, facilitating earlier activation during ESD events while maintaining non-operational status during normal circuit operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional NMOS transistors use implants for ESD protection, then ESD protection is achieved, but fabrication complexity and cost increase

Engineering Contradiction:

ImproveESD protectionVSAvoidfabrication complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent removes the implant step from the fabrication process entirely. The ESD protection function is achieved through the intrinsic properties of the transistor structure itself, specifically through the interaction between the first PP region and the gate stack, eliminating the need for separate implant procedures and associated masks.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The transistor structure provides its own ESD protection through the first PP region's interaction with the gate stack. The first PP region automatically triggers the ESD protection mechanism when voltage thresholds are exceeded, without requiring external implantation to activate protective functions.

Inventive Principle:

Principle #25Self-service

2Reliability

If conventional NMOS transistors use implants, then ESD protection is provided, but trigger voltage control and holding voltage management are insufficient

Engineering Contradiction:

ImproveESD protectionVSAvoidtrigger voltage control

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The first PP region is strategically positioned between the first NP region and the gate stack, creating a localized high-doping region with specific electrical properties. This local structural modification enables precise control over trigger voltage and holding voltage characteristics without affecting the entire device uniformly.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent controls ESD characteristics by adjusting the doping concentration and spatial distribution of the first PP region. By modifying parameters such as the depth, width, and doping level of the first PP region, the trigger voltage and holding voltage can be precisely tuned to desired values.

Inventive Principle:

Principle #35Parameter changes

3Ease of manufacture

If NMOS transistor structure is simplified without implants, then fabrication is easier, but trigger voltage reduction and holding voltage increase are not achieved

Engineering Contradiction:

Improvefabrication simplicityVSAvoidESD performance

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The transistor is divided into distinct functional regions including the first NP region, first PP region, second NP region, and gate stack. The first PP region acts as a separate ESD protection element within the overall structure, enabling independent optimization of ESD characteristics without complicating the fabrication process.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The first PP region serves as an intermediary element between the first NP region and the gate stack. It mediates the electrical interaction between these components, enabling voltage triggering and holding functions through its unique doping characteristics and spatial positioning.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS9929143B2N-type metal oxide semiconductor (NMOS) transistor for electrostatic discharge (ESD)

Publication Date: 2018.03.27 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

One or more techniques or systems for forming an n-type metal oxide semiconductor (NMOS) transistor for electrostatic discharge (ESD) are provided herein. In some embodiments, the NMOS transistor includes a first region, a first n-type plus (NP) region, a first p-type plus (PP) region, a second NP region, a second PP region, a shallow trench isolation (STI) region, and a gate stack. In some embodiments, the first PP region is between the first NP region and the second NP region. In some embodiments, the second NP region is between the first PP region and the second PP region, the gate stack is between the first PP region and the second NP region, the STI region is between the second NP region and the second PP region. Accordingly, the first PP region enables ESD current to discharge based on a low trigger voltage for the NMOS transistor.