Compressively Stressed Metal Gate Stack for NMOS Tensile Stress
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Solution Overview
Problem
Integrated circuits face challenges in enhancing on-state current in n-channel metal oxide semiconductor (NMOS) transistors while maintaining performance of p-channel metal oxide semiconductor (PMOS) transistors, as existing methods struggle to apply tensile stress to NMOS transistors without degrading PMOS transistors.
Innovation Solution
A gate stack for NMOS transistors is introduced, comprising an undoped polysilicon layer, an n-type polysilicon layer, a compressively stressed metal layer, and a third polysilicon layer, which induces tensile stress in the channel region and reduces dopant diffusion, while being compatible with anneal processes and photolithographic processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a metal layer is deposited to induce stress in NMOS transistors, then on-state current is improved, but fabrication complexity increases
Solution Approach 1:
The gate stack is segmented into distinct functional layers: undoped polysilicon layer, n-type polysilicon layer, compressively stressed metal layer, and third polysilicon layer. Each layer serves a specific purpose - the undoped and n-type polysilicon layers establish the work function, the metal layer provides compressive stress that translates to tensile stress in the channel, and the third polysilicon layer provides a silicon surface for metal silicide formation. This segmentation allows independent optimization of each layer's properties
Solution Approach 2:
The gate stack employs a composite structure combining multiple materials with different properties: polysilicon for work function control, metal (such as tungsten, molybdenum, titanium nitride, or tantalum nitride) for stress induction, and silicon for silicide formation. The metal layer is specifically chosen to be compatible with anneal processes and to generate appropriate stress without causing dopant diffusion, creating a composite material system that achieves multiple objectives simultaneously
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves on-state current in NMOS transistors without degrading PMOS transistors, facilitating efficient fabrication and performance in complementary metal oxide semiconductor (CMOS) integrated circuits.
Implementation Method 1
a layer of metal over the n-type polysilicon layer, which is under compressive stress, and generates tensile stress in the channel region of the NMOS transistor
Implementation Method 2
reduces diffusion of dopants from the lower layers of polysilicon to the upper layer of polysilicon
Data Source
AI summary
A gate stack for an NMOS transistor in an IC to induce tensile stress in the NMOS channel is disclosed. The gate stack includes a first layer of undoped polysilicon, a second layer of n-type polysilicon to establish a desired work function in the gate, layer of compressively stressed metal, and a third layer of polysilicon to provide a silicon surface for subsequent formation of metal silicide. Candidates for the compressively stressed metal are TiN, TaN, W, and Mo. In a CMOS IC, the n-type polysilicon layer and metal layer are patterned in NMOS transistor areas, while the first polysilicon layer and third polysilicon layer are patterned in both NMOS and PMOS transistor areas. Polysilicon CMP may be used to reduce topography between the NMOS and PMOS gate stacks to facilitate gate pattern photolithography.