NMOS Indium Retrograde Doping for Leakage Control
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Solution Overview
Problem
Indium implants in NMOS devices struggle to achieve the required solid solubility for targeting small leakage currents at nanometer scales, as they reach a solubility limit below the concentration needed for worst-case leakage currents, especially at device sizes less than 100 nanometers.
Innovation Solution
Implementing multiple Indium implants with varying energies (between 60 and 100 keV) to create retrograde profiles that provide higher threshold voltage and reduced short-channel effects, with surface doping kept low to minimize impurity scattering, allowing for deeper and more extensive Indium doping across the channel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single Indium implant is used, then the manufacturing process is simple, but the leakage current control is insufficient because Indium reaches solid solubility limit below the concentration required for worst case leakage currents
Solution Approach 1:
The single Indium implant process is segmented into multiple implants with different energies. The first implant uses 60-80 keV energy to create a retrograde profile, and the second implant uses 80-100 keV energy to achieve deeper doping. This segmentation allows each implant to target specific depth ranges, collectively achieving the required concentration profile that exceeds the solid solubility limit while maintaining process control.
Solution Approach 2:
The implant process changes key parameters including energy (60-100 keV range), dose (1×10^13 to 1×10^14 atoms/cm² per implant), and timing (sequential vs. simultaneous). By varying these parameters across multiple implants, the process achieves deeper Indium penetration and higher peak concentrations that would be impossible with a single implant, thereby controlling leakage current in sub-100nm devices.
2Reliability
If high surface doping is used, then the Indium concentration is sufficient to reduce leakage, but impurity scattering increases reducing device performance
Solution Approach 1:
The doping concentration is made non-uniform with depth, creating local quality variations. The retrograde profile achieved by the first implant (60-80 keV) places moderate Indium concentration at the surface while concentrating higher doses at deeper regions (20-50 nm depth). This local differentiation reduces surface impurity scattering while maintaining sufficient bulk concentration for leakage control.
Solution Approach 2:
The doping strategy transitions from surface-dominated to depth-dominated Indium distribution. By using multiple energy levels, the process creates a three-dimensional concentration profile where the peak Indium concentration occurs at depths of 20-50 nm rather than at the surface. This dimensional shift in doping distribution reduces surface scattering effects while achieving the required leakage control through deeper concentration accumulation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables NMOS devices to achieve higher threshold voltage and reduced short-channel effects, effectively targeting small leakage currents (on the order of 40 nanoamps) at nanometer scales, surpassing the limitations of single Indium implants.
Implementation Method 1
a first Indium (In) implant that is shallower than a gate dielectric thickness of the gate stack with a dose of between 1×10^13 cm^-2 to 1×10^14 cm^-2 and an energy between 60 and 80 keV
Data Source
AI summary
An integrated circuit (IC) includes at least one NMOS transistor, wherein the NMOS transistor includes a substrate having a semiconductor surface, and a gate stack formed in or on the surface including a gate electrode on a gate dielectric, wherein a channel region is located in the semiconductor surface below the gate dielectric. A source and a drain region are on opposing sides of the gate stack. An In region having a retrograde profile is under at least a portion of the channel region. The retrograde profile includes (i) a surface In concentration at a semiconductor surface interface with the gate dielectric of less than 5×1016 cm−3, (ii) a peak In concentration at least 20 nm from the semiconductor surface below the gate dielectric, and wherein (iii) the peak In concentration is at least two (2) orders of magnitude higher than the In concentration at the semiconductor surface interface. A method to form an IC including at least one NMOS transistor includes implanting a first In implant at a first energy and a second In implant at a second energy, wherein the first In implant together with the second In implant form an In region having a retrograde profile under at least a portion of the channel region, and wherein the second energy is at least 5 keV more than the first energy.