NMOS LDO Topology for Higher PSRR and Smaller IC Area
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Solution Overview
Problem
P-type metal-oxide-semiconductor (PMOS) low dropout (LDO) voltage regulators in wireless communication devices do not provide sufficient power supply rejection ratio (PSRR) or reduction in supply noise, and they consume a large physical area on integrated circuits.
Innovation Solution
The use of an N-type metal-oxide-semiconductor (NMOS) LDO voltage regulator with an N-type pass transistor, which offers improved PSRR, increased bandwidth, and reduced physical size compared to PMOS LDOs, achieved through a specific topology and compensation capacitor design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a PMOS LDO voltage regulator is used, then the device can generate various voltage levels for integrated circuits, but the power supply rejection ratio (PSRR) and reduction in supply noise are insufficient
Solution Approach 1:
The patent changes the transistor type parameter from PMOS to NMOS in the LDO regulator architecture. This parameter change fundamentally alters the electrical characteristics, enabling superior power supply rejection ratio and noise performance while maintaining the voltage regulation function for integrated circuits.
2Ease of operation
If a PMOS LDO voltage regulator is used, then voltage levels can be generated for various functions, but the physical area consumed on integrated circuits is relatively large
Solution Approach 1:
The patent changes the transistor type parameter from PMOS to NMOS, which has inherently smaller device area for equivalent current handling capabilities. This parameter change reduces the physical footprint of the LDO regulator on the integrated circuit while preserving its voltage generation functionality.
3Reliability
If an NMOS LDO voltage regulator is used, then improved PSRR and noise rejection are achieved, but the circuit topology becomes more complex with additional transistors and compensation capacitors
Solution Approach 1:
The patent segments the LDO regulator into distinct functional blocks: an error amplifier stage with differential inputs, a compensation network with dedicated capacitors, and an NMOS pass transistor stage. This segmentation allows each block to be optimized independently for performance while managing overall circuit complexity.
Solution Approach 2:
The patent introduces compensation capacitors as intermediary elements between the error amplifier and the output stage. These capacitors mediate the frequency compensation function, stabilizing the feedback loop and enabling the complex NMOS topology to achieve superior PSRR without oscillation.
Data Source
AI summary
Embodiments disclosed herein relate to a low-voltage dropout regulator and more specifically to improving a power supply rejection ratio (PSRR) of the low dropout voltage regulator. The low dropout voltage regulator may be used to generate various voltages for integrated circuits of an electronic device. In some cases, a P-type metal-oxide-semiconductor (PMOS) low dropout (LDO) voltage regulator may be used. However, the PMOS LDO may not provide a sufficient PSRR or reduction in supply noise. To address these issues, an N-type metal-oxide-semiconductor (NMOS) LDO voltage regulator having an NMOS pass transistor may be used. The NMOS LDO may provide a lower impedance than the PMOS LDO. Further, the NMOS LDO may provide an increased bandwidth and consume a smaller physical area than the PMOS LDO.