NMOS Super Source Follower LDO for Higher PSRR and Smaller Area
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Solution Overview
Problem
P-type metal-oxide-semiconductor (PMOS) low dropout (LDO) voltage regulators in wireless communication devices do not provide sufficient power supply rejection ratio (PSRR) or reduction in supply noise, and they consume a large physical area on integrated circuits.
Innovation Solution
An N-type metal-oxide-semiconductor (NMOS) LDO voltage regulator with an N-type pass transistor is used, featuring a similar topology to PMOS LDO but with improved PSRR, increased bandwidth, and reduced physical size, utilizing a current source, compensation capacitor, and specific transistor configurations to enhance noise rejection and power supply rejection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a PMOS LDO voltage regulator is used, then the device can generate various voltage levels for integrated circuits, but the power supply rejection ratio (PSRR) is insufficient and supply noise is not adequately reduced
Solution Approach 1:
The patent inverts the conventional PMOS LDO architecture by using an NMOS pass transistor instead of a PMOS transistor. This inversion allows the regulator to achieve superior PSRR and noise rejection characteristics. The NMOS transistor's lower on-resistance and different noise profile compared to PMOS devices enable the circuit to better reject supply noise and provide higher power supply rejection ratio, directly resolving the technical contradiction.
Solution Approach 2:
The patent changes key electrical parameters of the LDO regulator by substituting the transistor type and adjusting associated circuit parameters. The NMOS transistor provides lower channel resistance and different capacitance characteristics compared to PMOS, which fundamentally changes the regulator's noise performance and PSRR. This parameter change enables the circuit to achieve the desired improvement in power supply rejection while maintaining voltage regulation functionality.
2Reliability
If a PMOS LDO voltage regulator is used, then voltage regulation can be achieved, but the physical area consumed on the integrated circuit is relatively large
Solution Approach 1:
By inverting from PMOS to NMOS transistor implementation, the patent achieves more space-efficient circuit design. The NMOS transistor requires smaller device area to achieve the same current driving capability due to its superior mobility characteristics. This inversion allows the LDO regulator to maintain full voltage regulation functionality while occupying less silicon real estate, directly addressing the area constraint.
3Reliability
If an NMOS LDO voltage regulator is used, then PSRR and noise rejection are improved, but the circuit topology becomes more complex
Solution Approach 1:
The patent demonstrates that inverting to NMOS topology actually simplifies certain aspects of the circuit design. The NMOS transistor's inherent characteristics allow for more straightforward compensation network design and fewer additional components are needed to achieve the desired noise rejection performance. The inversion enables direct coupling configurations that reduce the number of stages required, thereby managing complexity while improving noise rejection.
Data Source
AI summary
Embodiments disclosed herein relate to a low-voltage dropout regulator and more specifically to improving a power supply rejection ratio (PSRR) of the low dropout voltage regulator. The low dropout voltage regulator may be used to generate various voltages for integrated circuits of an electronic device. In some cases, a P-type metal-oxide-semiconductor (PMOS) low dropout (LDO) voltage regulator may be used. However, the PMOS LDO may not provide a sufficient PSRR or reduction in supply noise. To address these issues, an N-type metal-oxide-semiconductor (NMOS) LDO voltage regulator having an NMOS pass transistor may be used. The NMOS LDO may provide a lower impedance than the PMOS LDO. Further, the NMOS LDO may provide an increased bandwidth and consume a smaller physical area than the PMOS LDO.