NMOS LDO PSRR Improvement via Ripple Cancellation

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Solution Overview

Problem

Conventional LDO voltage regulators with N-channel pass transistors face challenges in achieving high PSRR at high frequencies due to the trade-off between transistor size and dropout voltage, and existing ripple cancellation techniques are not effective for N-channel transistors, especially when operating in the linear region.

Innovation Solution

The implementation of an N-channel cancellation transistor and an AC current gain circuit that generates a cancellation current equal and opposite to the ripple current, canceling it at the gate of the pass transistor to prevent ripple voltage from being passed onto the output, thereby improving PSRR independently of the pass transistor's operating region.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the size of the N-channel pass transistor is increased to improve PSRR, then power supply rejection ratio is improved, but the dropout voltage increases and the transistor cannot operate in deep linear region

Engineering Contradiction:
ImprovePSRRVSAvoiddropout voltage
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent introduces a cancellation transistor as an intermediary element that generates a current to counteract the ripple current flowing through the pass transistor's gate-drain capacitance. This mediator transistor (MN3) receives the input ripple voltage and produces a cancellation current that is injected back into the gate node, effectively canceling the harmful displacement current without requiring the pass transistor to be oversized.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent applies preliminary anti-action by proactively generating a cancellation current that opposes the ripple current before it can significantly affect the output. The cancellation transistor is configured to produce a current equal and opposite to the displacement current through the pass transistor's parasitic capacitance, preventing the ripple voltage from being amplified and passed to the output.

Inventive Principle:
Principle #9Preliminary anti-action

2Use of energy by moving object

If the size of the N-channel pass transistor is reduced to lower dropout voltage, then headroom is improved, but PSRR deteriorates due to operation far from saturation region

Engineering Contradiction:
Improvedropout voltageVSAvoidPSRR
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The cancellation transistor serves as a mediator that compensates for the poor intrinsic PSRR of small transistors. By injecting a cancellation current that counteracts the ripple current, the system achieves high PSRR even when the pass transistor is small and operating in the deep linear region, eliminating the need for large transistor sizes.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent changes the operating parameters by allowing the pass transistor to operate in the deep linear region (far from saturation) while maintaining high PSRR through the cancellation mechanism. The cancellation transistor's transconductance and the feedback network are designed to provide the necessary current amplification to achieve effective ripple cancellation across different operating conditions.

Inventive Principle:
Principle #35Parameter changes

3Ease of operation

If an external biasing voltage rail is used to drive the gate of N-channel pass transistor, then gate drive capability is improved, but system complexity increases

Engineering Contradiction:
Improvegate drive capabilityVSAvoidsystem complexity
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The error amplifier is designed to perform multiple functions: it provides the gate drive voltage for the pass transistor and simultaneously generates the cancellation current through its interaction with the cancellation transistor network. This multi-functional approach eliminates the need for separate biasing circuits while maintaining adequate gate drive capability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the gate drive function and the ripple cancellation function into a single integrated circuit architecture. The error amplifier, cancellation transistor, and feedback network work together as a unified system, combining what would traditionally be separate functions into one cohesive structure that reduces overall system complexity.

Inventive Principle:
Principle #5Merging (Combining)

4Device complexity

If an on-chip charge pump is used to generate gate drive voltage, then integration is improved, but switching noise is introduced and die area increases

Engineering Contradiction:
ImproveintegrationVSAvoidswitching noise
Core Design Contradiction:
Device complexityVSObject-generated harmful factors

Solution Approach 1:

The cancellation transistor acts as an intermediary that specifically targets and cancels the switching noise generated by the charge pump. By generating a cancellation current that is equal and opposite to the charge pump's switching current, the system suppresses the harmful noise without eliminating the charge pump's useful gate drive function.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent converts the harmful switching noise from the charge pump into a beneficial cancellation signal. The cancellation network is designed to detect the charge pump's switching current and generate an opposing current that neutralizes the noise, effectively transforming the harmful effect into a useful ripple reduction mechanism.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Data Source

PatentUS9577508B2NMOS LDO PSRR improvement using power supply noise cancellation
Publication Date: 2017.02.21 TEXAS INSTRUMENTS INC
  • US9577508B2 patent drawing
  • US9577508B2 patent drawing
  • US9577508B2 patent drawing

AI summary

Power-supply ripple rejection (PSRR) at high frequencies is improved for an LDO voltage regulator with an NMOS pass transistor (MN1). A ripple voltage (Vripple) present on the input voltage causes a ripple current (Iripple) through parasitic gate-drain capacitance of the pass transistor. A small ripple current (Ifraction) proportional to the ripple current (Iripple) is generated and amplified to generate a cancellation current (Icancel). The cancellation current is drawn from the gate of NMOS pass transistor (MN1) to cancel the ripple current so that no net ripple current flows through the finite output impedance of an error amplifier (2), to thereby achieve the PSRR improvement.