Adjusting NMOS Metal Gate Work Function via Ion Implantation
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Solution Overview
Problem
In semiconductor technology, integrating a metal gate with a high K dielectric in CMOS devices beyond 45 nm poses challenges such as thermal stability and interfacial states, particularly in achieving an appropriate low threshold voltage due to the Fermi level pinning effect.
Innovation Solution
A method involving the formation of an interfacial oxide layer, deposition of a high dielectric constant gate dielectric film, and ion implantation of metal ions into the metal gate electrode to adjust the work function, utilizing rapid thermal annealing and PVD processes, ensuring compatibility with conventional CMOS processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a conventional SiO2/poly-Si gate stack structure is used, then the fabrication process is simple, but tunneling current and resistance increase and depletion effect occurs
Solution Approach 1:
The patent employs a composite gate stack structure consisting of high-K dielectric material (such as HfO2) combined with a metal gate electrode. This composite structure leverages the high dielectric constant of HfO2 to maintain electrical control while using the metal gate to eliminate depletion effects and reduce tunneling current, thereby improving device reliability without significantly complicating the fabrication process
2Reliability
If a metal gate with high K dielectric is integrated, then tunneling current and resistance are reduced, but thermal stability and interfacial states become problematic
Solution Approach 1:
The patent optimizes the metal gate composition by adjusting the ratio of metal elements (such as Ti, Al, Mo) in the composite metal gate stack. By changing the compositional parameters and performing controlled annealing treatments, the patent achieves a balance between work function adjustment and thermal stability, ensuring the gate structure maintains its integrity during subsequent high-temperature CMOS fabrication steps
3Reliability
If a metal gate with high K dielectric is used, then Fermi level pinning effect is alleviated, but achieving appropriate low threshold voltage remains challenging
Solution Approach 1:
The patent implements a multi-layer metal gate structure where different metal materials are stacked to create localized functional zones. The bottom metal layer (e.g., TiN) provides good interface characteristics with the high-K dielectric, while the top metal layer (e.g., Al, Mo) is selected to achieve the desired work function and threshold voltage. This local differentiation of material properties enables precise threshold voltage control while maintaining high device reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively adjusts the metal gate work function, achieving an appropriate threshold voltage with good thermal stability and compatibility with industrial CMOS processes, as demonstrated by the shift in C-V characteristic curves indicating reduced work function and improved device performance.
Implementation Method 1
the interfacial oxide layer of SiOx or SiON is formed by rapid thermal oxidation at a temperature of 600-900° C. for 20-120 s
Implementation Method 2
a HfLaON film is deposited by alternately sputtering a Hf—La target and a Hf target, or a HfSiON gate dielectric is deposited by alternately sputtering a Hf target and a Si target, by means of magnetic-controlled reactive sputtering
Implementation Method 3
performing rapid thermal annealing after depositing of the high dielectric constant gate dielectric film, wherein the rapid thermal annealing is performed at a temperature of 600-1050° C. for 10-120 s
Implementation Method 4
doping the metal nitride gate by implanting N-type metal ions
Implementation Method 5
performing thermal annealing at a temperature of 350-1050° C.
Implementation Method 6
forming alloy, in which annealing for alloying is performed in an oven filled with N2 or (N7+10% H2) at a temperature of 380-450° C. for 30-60 minutes
Data Source
AI summary
A method of adjusting a metal gate work function of an NMOS device comprises: depositing a layer of metal nitride film or metal film on a high K dielectric as a metal gate electrode by a physical vapor deposition process; implanting elements such as Tb, Er, Yb or Sr into the metal gate electrode by an ion implantation process; performing a high temperature annealing so that the doped metal ions are driven to and accumulate on the interface between the metal gate electrode and the high K gate dielectric, or form dipoles by an interface reaction on the interface between the high K gate dielectric and SiO2. The method is capable of adjusting the metal gate work function, and is well-compatible with CMOS process.