NMOS Multiplexer Bit Line Pre-Charge Circuit
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Solution Overview
Problem
Existing SRAM memory designs face challenges in reducing power consumption while maintaining stability and efficiency, particularly in deep sub-micron technologies, where increased complexity and area consumption are concerns due to hierarchical bit line arrangements and sense amplifier variability.
Innovation Solution
The use of an NMOS-only multiplexer circuit for bit line control, which pre-charges bit lines concurrently using NMOS devices and PMOS devices for voltage supply, allows for reduced power consumption and improved stability by eliminating the need for additional area-consuming interface circuitry and sense amplifiers, while also enabling efficient bit line equilibration between memory accesses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If traditional pre-charge circuits using PMOS devices connected to every bit line are used, then bit lines can be pre-charged to VDD, but area consumption increases and power consumption increases
Solution Approach 1:
The patent combines the pre-charge function and multiplexer function into a single circuit structure. The NMOS transistors serve dual purposes: they act as switches for selecting bit lines and simultaneously function as pre-charge devices by connecting selected bit lines to VDD through their drain-gate connections. This eliminates the need for separate pre-charge PMOS devices, reducing both area and power consumption while maintaining the pre-charge functionality.
2Use of energy by stationary object
If hierarchical bit line arrangements are implemented, then power consumption is reduced, but device complexity and area consumption increase due to additional interface circuitry
Solution Approach 1:
The NMOS transistors in the multiplexer circuit perform multiple functions simultaneously: bit line selection switching, pre-charging, and equilibration. This multi-functionality eliminates the need for additional interface circuitry between local and global bit lines, reducing device complexity while maintaining the power benefits of hierarchical arrangements.
3Measurement precision
If sense amplifiers are added to interface local and global bit lines, then reading capability is improved, but area consumption and device complexity increase
Solution Approach 1:
The patent merges the pre-charge function with the multiplexer switching function in the same NMOS transistors. By utilizing the inherent capacitance and voltage characteristics of the NMOS devices already present in the multiplexer, the circuit achieves both selection and pre-charge capabilities without requiring additional sense amplifier circuitry, thereby reducing area consumption while maintaining reading capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption and maintains performance without increasing area consumption, stabilizes memory cell operations, and simplifies the design of sense amplifiers by using the same NMOS devices for pre-charging and sensing, effectively addressing the limitations of traditional bit line pre-charge schemes.
Implementation Method 1
The switch consists of an NMOS device. A multiplexer controller is configured to be able to separately select each pair of bit lines by activating the associated NMOS devices using the corresponding bit line selection signals, and is configured to select all of the pairs of bit lines connected to the data input and output circuitry simultaneously when pre-charging the bit lines such that all of the bit lines connected to the data input and output circuitry are pre-charged concurrently via the NMOS devices.
Implementation Method 2
pre-charges bit lines concurrently using NMOS devices and PMOS devices for voltage supply
Data Source
AI summary
There is provided a memory unit (100). The memory unit comprises a plurality of memory cells (110), each memory cell of the plurality of memory cells being operatively connected to data input and output circuitry by a pair of bit lines (130a, 130b), a pre-charge circuit (150) configured to provide a voltage for charging the bit lines, and a multiplexer circuit. The multiplayer circuit (140) comprises, for each bit line, an associated NMOS (142a, 142b) device that is configured to selectively connect the bit line (130a, 130b) to the data input and output circuitry and to the pre-charge circuit (150) when activated by a corresponding bit line selection signal, and a multiplex controller (144) that is configured to be able to select each pair of bit lines by activating the associated NMOS devices (142a, 142b) using the corresponding bit lines selection signals.