NMOS and PMOS Epitaxial Isolation in NSFET and FinFET Regions
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Solution Overview
Problem
As semiconductor devices continue to reduce minimum feature sizes for increased integration density, challenges arise in achieving independent control of epitaxial structures in NMOS and PMOS regions, leading to device defects and reduced performance.
Innovation Solution
The formation of nanostructure and fin field-effect transistors (NSFETs and FinFETs) on a wafer using masking steps during etching and epitaxial growth, allowing independent control of epitaxial structures in NMOS and PMOS regions, enhancing design flexibility and reducing device defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but additional problems arise that reduce device performance and reliability
Solution Approach 1:
The patent divides the semiconductor wafer into separate NMOS and PMOS regions with distinct epitaxial processing sequences. Each region receives tailored epitaxial growth conditions, allowing independent optimization of device characteristics while maintaining high integration density across the entire wafer.
Solution Approach 2:
Different epitaxial structures are formed in different regions of the wafer - NMOS regions receive one type of epitaxial treatment while PMOS regions receive another. This local differentiation allows each transistor type to have optimized performance characteristics despite the reduced minimum feature sizes.
2Ease of manufacture
If conventional epitaxial processing is used without region-specific masking, then processing is simpler and faster, but independent control of epitaxial structures in NMOS and PMOS regions cannot be achieved, leading to device defects
Solution Approach 1:
Masking structures are formed in advance before epitaxial growth to predefine the regions that will receive different epitaxial treatments. This preliminary masking enables precise spatial control of epitaxial structures in NMOS and PMOS regions, preventing device defects while maintaining efficient processing.
Solution Approach 2:
Photomask layers serve as intermediary structures that selectively block or permit epitaxial material deposition in specific regions. These masking intermediaries enable independent control of epitaxial growth in NMOS and PMOS areas without complicating the overall processing sequence.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves device performance by providing greater design flexibility and reducing defects in semiconductor devices, particularly in NMOS and PMOS regions.
Implementation Method 1
masking steps during etching and epitaxial growth, allowing independent control of epitaxial structures in NMOS and PMOS regions
Data Source
AI summary
A method of independently forming source/drain regions in NMOS regions including nanosheet field-effect transistors (NSFETs), NMOS regions including fin field-effect transistors (FinFETs) PMOS regions including NSFETs, and PMOS regions including FinFETs and semiconductor devices formed by the method are disclosed. In an embodiment, a device includes a semiconductor substrate; a first nanostructure over the semiconductor substrate; a first epitaxial source/drain region adjacent the first nanostructure; a first inner spacer layer adjacent the first epitaxial source/drain region, the first inner spacer layer comprising a first material; a second nanostructure over the semiconductor substrate; a second epitaxial source/drain region adjacent the second nanostructure; and a second inner spacer layer adjacent the second epitaxial source/drain region, the second inner spacer layer comprising a second material different from the first material.