NMOS PMOS Gate Stack Work Function Tailoring via Selective Etching
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Solution Overview
Problem
Current semiconductor fabrication methods require separate process steps for NMOS and PMOS transistors, and there is a need to tailor the work functions of transistors for specific applications while simultaneously forming portions of both types of transistors.
Innovation Solution
A method involving a semiconductor substrate with defined NMOS and PMOS regions, where a silicon-containing material is formed across both regions, thinned over the NMOS region using tetramethylammonium hydroxide to a thickness of less than or equal to 30 angstroms, and selectively removed from the PMOS region using ammonium hydroxide, allowing for the formation of tailored gate stacks for NMOS and PMOS transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate process steps are used for NMOS and PMOS transistors, then each transistor type can be optimized independently, but the total number of process steps increases and productivity decreases
Solution Approach 1:
The invention segments the gate stack formation process by selectively removing silicon-containing material from PMOS regions while retaining it in NMOS regions. This allows different transistor types to be optimized independently through selective material removal and subsequent processing steps, enabling tailored work functions for each transistor type within a unified fabrication sequence.
Solution Approach 2:
The invention applies local quality by creating region-specific gate structures: NMOS regions retain thin silicon-containing material layers (≤30 Å) for optimized NMOS performance, while PMOS regions have the silicon-containing material completely removed for tailored PMOS characteristics. This local differentiation enables independent optimization of each transistor type without requiring separate fabrication processes.
2Productivity
If common process steps are used for NMOS and PMOS transistors, then productivity improves and process steps are reduced, but the ability to tailor work functions for specific applications is limited
Solution Approach 1:
The invention enables work function tailoring within common process steps by selectively removing silicon-containing material from PMOS regions while retaining it in NMOS regions. The retained silicon-containing material in NMOS regions modifies the work function to optimize NMOS performance, while its removal from PMOS regions allows independent PMOS work function optimization through subsequent processing, achieving application-specific tailoring without sacrificing productivity.
Solution Approach 2:
The invention applies preliminary action by forming a silicon-containing material layer across both NMOS and PMOS regions before selective removal. This preliminary formation creates a foundation that can be differentially processed: the layer is completely removed from PMOS regions and selectively retained/thinned in NMOS regions, enabling work function tailoring for both transistor types within a unified process sequence.
3Speed
If thin silicon-containing layers are incorporated in NMOS gate stacks, then high-frequency response is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The invention applies preliminary action by first forming a thicker silicon-containing material layer that can be more easily deposited with uniform thickness and better process control. Subsequently, this pre-formed layer is selectively thinned to the target thickness of ≤30 Å in NMOS regions through controlled removal processes. This two-step approach (form thick, then thin selectively) improves high-frequency response while maintaining manufacturability by decoupling the deposition precision requirements from the final thin thickness specification.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the simultaneous fabrication of NMOS and PMOS transistors with tailored work functions, reducing process steps and improving high-frequency response by incorporating thin silicon-containing layers within the NMOS gate stacks.
Implementation Method 1
Ammonium hydroxide is utilized to remove the silicon-containing material from over the PMOS region
Implementation Method 2
Tetramethylammonium hydroxide is utilized to thin the silicon-containing material over the NMOS region
Data Source
AI summary
The invention includes methods of forming PMOS transistors and NMOS transistors. The NMOS transistors can be formed to have a thin silicon-containing material between a pair of metal nitride materials, while the PMOS transistors are formed to have the metal nitride materials directly against one another. The invention also includes constructions which contain an NMOS transistor gate stack having a thin silicon-containing material between a pair of metal nitride materials. The silicon-containing material can, for example, consist of silicon, conductively-doped silicon, or silicon oxide; and can have a thickness of less than or equal to about 30 angstroms.