NMOS Shift Register for Narrow Bezel Displays
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Solution Overview
Problem
Existing shift registers in display panels require excessive transistors, making it difficult to achieve a narrow bezel design due to the use of both PMOSFETs and NMOSFETs, leading to high power consumption and complex manufacturing processes.
Innovation Solution
A shift register design utilizing only NMOSFET transistors with a compact configuration, including a pull-up circuit, pull-down circuit, and bidirectional selection circuit, which controls electrical connections based on clock signals to reduce power consumption and simplify manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If both PMOSFETs and NMOSFETs are used in the shift register, then the shift register can achieve proper logic level control, but the number of transistors increases and the device area expands
Solution Approach 1:
The patent applies homogeneity by using only NMOSFETs throughout the shift register circuit, eliminating the need for PMOSFETs. This is achieved by designing the pull-up circuit using NMOSFETs with enhanced drive capability, allowing the entire circuit to be constructed with a single transistor type, thereby reducing device area while maintaining proper logic level control
Solution Approach 2:
The patent changes the parameters of the NMOSFETs by adjusting their width-to-length ratios to achieve different drive strengths. The pull-up NMOSFETs are designed with larger W/L ratios to provide sufficient pull-up current, while other NMOSFETs use smaller ratios for proper signal levels, enabling the circuit to function with only NMOSFETs
2Reliability
If both PMOSFETs and NMOSFETs are used in the shift register, then the circuit can maintain proper voltage levels, but the manufacturing process becomes more complex
Solution Approach 1:
The patent simplifies manufacturing by using only NMOSFETs, which requires only a single photo-mask layer for transistor formation. This eliminates the need for separate PMOSFET fabrication processes, reducing manufacturing complexity while maintaining voltage level stability through properly designed NMOSFET pull-up circuits
3Reliability
If the shift register uses a conventional design with multiple transistor types, then proper signal levels can be maintained, but power consumption increases
Solution Approach 1:
The patent optimizes power consumption by carefully selecting the W/L ratios of NMOSFETs to achieve proper signal levels without excessive current draw. The pull-up NMOSFETs are sized to provide sufficient current for fast transitions while remaining efficient, and the clock signal timing is optimized to minimize simultaneous conduction of opposing switches, reducing dynamic power consumption
4Area of stationary object
If the shift register uses only NMOSFETs, then the device area is reduced and manufacturing is simplified, but achieving proper pull-up capability becomes more difficult
Solution Approach 1:
The patent achieves proper pull-up capability with NMOSFETs by increasing the W/L ratio of the pull-up transistors and optimizing their positioning in the circuit. The pull-up NMOSFETs are designed with larger channel widths to provide sufficient drive current for rapid signal transitions, compensating for the generally weaker pull-up capability of NMOSFETs compared to PMOSFETs
Data Source
AI summary
A shift register has a first switch, a pull-up circuit, and a pull-down circuit. The first switch receives a first clock signal. The pull-up circuit is configured to turn on the first switch to pull up a voltage level of an output terminal of the shift register. The pull-up circuit has a second switch and a first control circuit. The first control circuit is coupled to a first system power terminal to avoid an excessive voltage difference between two nodes of the first control circuit. The pull-down circuit is configured to pull down the voltage level of the output terminal of the shift register when the first switch is turned off, and further configured to keep a voltage level of a control node of a switch coupled between the output terminal and a second system power terminal at a low voltage.