NMOS Snap-Back Prevention via Auxiliary Bias Circuit
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Solution Overview
Problem
As integrated circuit feature sizes shrink, the breakdown of reverse bias junctions at high voltages leads to damaging leakage currents in MOS transistors, particularly in the gate-drain junction of NMOS transistors, exacerbating snap-back current issues, which can reduce voltage delivery to loads and cause reliability problems.
Innovation Solution
The solution involves connecting a second NMOS transistor in series with the first NMOS transistor and coupling its gate node to a bias node, while an auxiliary circuit provides a bias potential at the source node of the first NMOS transistor when it is in the OFF state, preventing the parasitic bipolar transistor from turning on and thus reducing the likelihood of snap-back current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If high voltages are applied to program memory devices, then programming capability is achieved, but breakdown in reverse bias junctions occurs causing damaging leakage current
Solution Approach 1:
A parasitic bipolar transistor is intentionally utilized as an intermediary mechanism to control and limit the leakage current that flows during high voltage programming operations. By designing the circuit to exploit the bipolar transistor's characteristics, the harmful leakage is converted into a controlled protective mechanism that prevents damage to the gate-drain junction.
Solution Approach 2:
The invention changes the electrical parameters of the circuit by introducing a parasitic bipolar transistor that alters the current-voltage characteristics. This enables the circuit to operate at high programming voltages while maintaining controlled leakage current through the bipolar transistor's inherent current amplification and limiting properties.
2Productivity
If feature sizes are decreased to increase transistor integration, then device density improves, but breakdown voltage decreases exacerbating snap-back current
Solution Approach 1:
The invention converts the harmful snap-back current effect, which becomes more severe with smaller feature sizes, into a beneficial protective mechanism. The parasitic bipolar transistor is designed to activate during snap-back conditions, using the high current density inherent in small-feature devices to trigger the bipolar transistor's current limiting action, thereby protecting the device.
Solution Approach 2:
The parasitic bipolar transistor is pre-configured in the circuit structure before operation, positioned to automatically activate when snap-back conditions occur. This preliminary arrangement ensures that the protective mechanism is already in place and will respond immediately when high current density conditions arise from small feature size operation.
3Reliability
If a parasitic bipolar transistor is utilized to control leakage current, then reliability improves, but device complexity increases
Solution Approach 1:
The parasitic bipolar transistor is formed using the same fabrication processes and structural elements already present in the CMOS device, requiring no additional manufacturing steps or external components. The transistor utilizes existing doped regions and material layers, allowing the circuit to self-regulate leakage current without adding external complexity to the device structure or fabrication process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents snap-back current in NMOS transistors by keeping the parasitic bipolar transistor in an OFF state, reducing the risk of leakage currents and ensuring reliable operation even at high voltages, thereby enhancing the reliability and performance of integrated circuits.
Implementation Method 1
breakdown in reversed bias junctions at sufficiently high voltages... breakdown voltage of gate-drain junction of MOS transistors... breakdown may result in a damaging leakage current
Data Source
AI summary
A method and a circuit for preventing snap-back current in NMOS transistors of MOS integrated circuits are provided. Example embodiments may include preventing snap-back current in a circuit including a first NMOS transistor having an associated parasitic bipolar transistor. A second NMOS transistor may be connected in series with the first NMOS transistor. A gate node of the second NMOS transistor may be coupled to a bias node, such that the second NMOS transistor in conductive (ON) state. An auxiliary circuit coupled to a source node of the first NMOS transistor may be configured to provide a bias potential at the source node of the first NMOS transistor, when the first NMOS transistor is in a non-conducting state (OFF).