NMOS Charging Protection Circuit With Sub Port Bias Control
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Solution Overview
Problem
Conventional charging protection circuits using two NMOS switching transistors in series for bidirectional blocking result in high internal losses and costs due to unidirectional blocking capability of MOS transistors, leading to increased internal resistance and substrate bias effects.
Innovation Solution
Employing a four-terminal NMOS switching transistor with a Sub port management circuit that includes a pull-up circuit to equalize the potential of the Sub port with the drain, reducing internal resistance and substrate bias effects, thereby minimizing losses and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If two NMOS switching transistors are used in series to implement bidirectional blocking, then bidirectional blocking capability is achieved, but internal losses and costs increase due to cumulative internal resistance
Solution Approach 1:
The patent merges the functions of two separate NMOS switching transistors into a single four-terminal NMOS switching transistor. This consolidation maintains the bidirectional blocking capability while reducing the cumulative internal resistance, thereby decreasing internal losses and energy consumption during charging operations.
Solution Approach 2:
The four-terminal NMOS switching transistor is designed to perform multiple functions that were previously required from two separate transistors. It provides bidirectional blocking, voltage control, and substrate bias management through its four terminals (source, drain, gate, and substrate), eliminating the need for additional components and reducing overall system losses.
2Adaptability or versatility
If two NMOS switching transistors are used in series for bidirectional blocking, then bidirectional charging is enabled, but costs increase due to additional components
Solution Approach 1:
The patent consolidates two separate NMOS switching transistor components into a single integrated four-terminal NMOS switching transistor. This merging reduces the total component count, simplifies the charging protection circuit, and lowers manufacturing costs while maintaining full bidirectional charging functionality.
Solution Approach 2:
The four-terminal NMOS switching transistor is designed as a universal component that handles both forward and reverse charging operations through its substrate terminal control. This multi-functional design eliminates the need for separate components for different charging directions, reducing overall circuit complexity and manufacturing expenses.
3Loss of energy
If Sub port potential is not managed, then substrate bias effect occurs increasing internal resistance, but adding Sub port management circuit increases device complexity
Solution Approach 1:
The patent integrates the Sub port management function directly into the four-terminal NMOS switching transistor structure itself. The substrate terminal is internally connected to the drain terminal through the transistor's inherent structure, eliminating the need for external Sub port management circuits while effectively controlling substrate bias and maintaining low internal resistance.
Solution Approach 2:
The four-terminal NMOS switching transistor automatically manages its own substrate bias through its internal structure. The substrate terminal is self-connected to the drain, creating an inherent feedback mechanism that maintains optimal bias conditions without requiring external control circuits, thereby reducing overall device complexity while controlling internal resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces internal losses and costs by utilizing a four-terminal NMOS switching transistor with a Sub port management circuit, effectively mitigating substrate bias effects and maintaining low on-resistance, thus enhancing efficiency and reducing component wear.
Implementation Method 1
floating management is further performed on potential of a Sub port of the first four-terminal NMOS switching transistor in the charging protection circuit, so that when the first four-terminal NMOS switching transistor is turned on, a voltage between the Sub port and a first drain that is in the first four-terminal NMOS switching transistor and that is connected to a first power supply interface is reduced, thereby weakening a substrate bias effect
Data Source
AI summary
This application relates to a charging protection circuit. The charging protection circuit implements overcurrent protection by using a four-terminal NMOS switching transistor. In the solution provided in this application, floating management is performed on a Sub port of the four-terminal NMOS switching transistor. Specifically, when the four-terminal NMOS switching transistor is turned on, potential of the Sub port is pulled up, to avoid an excessively large internal resistance of the four-terminal NMOS switching transistor caused by an excessively large voltage between the Sub port and a drain of the four-terminal NMOS switching transistor. In addition, this application further provides a charging circuit and an electronic device.