NMOS High-Frequency Switch Back-Gate Biasing for Better Isolation
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Solution Overview
Problem
Conventional high-frequency switches using field effect transistors (FETs) experience signal leakage through parasitic capacitance during the cut-off state due to open-circuit impedance, leading to degraded isolation.
Innovation Solution
A high-frequency switch with a resistive element between the back gate and high-frequency ground, and a first switching circuit that creates a short circuit between the back gate and high-frequency ground upon cut-off, utilizing a parasitic diode formed at the junction surface between the N-well and back gate of an NMOS transistor to control bias potential.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a resistive element is disposed between the back gate and high-frequency ground to maintain constant Vgb, then signal distortion is avoided, but signal leakage occurs through parasitic capacitance during cut-off state
Solution Approach 1:
The patent applies the dynamics principle by making the impedance of the back gate dynamic rather than static. A switching circuit is introduced that changes the connection state of the back gate based on the operation state (conduction or cut-off) of the main transistor. During conduction, the back gate is connected to high-frequency ground through a resistive element to maintain constant Vgb and prevent signal distortion. During cut-off, the back gate is disconnected from the resistive element, allowing its potential to follow source/drain fluctuations, which prevents signal leakage through parasitic capacitance. This dynamic impedance adjustment resolves the contradiction between preventing signal distortion and preventing signal leakage.
2Reliability
If the back gate has open-circuit impedance during cut-off to maintain constant Vgb, then signal distortion is prevented, but isolation between source and drain is degraded
Solution Approach 1:
The patent applies the dynamics principle by making the impedance of the back gate dynamic rather than static. A switching circuit is introduced that changes the connection state of the back gate based on the operation state (conduction or cut-off) of the main transistor. During conduction, the back gate is connected to high-frequency ground through a resistive element to maintain constant Vgb and prevent signal distortion. During cut-off, the back gate is disconnected from the resistive element, allowing its potential to follow source/drain fluctuations, which prevents signal leakage through parasitic capacitance. This dynamic impedance adjustment resolves the contradiction between preventing signal distortion and preventing signal leakage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses signal leakage and improves isolation during the cut-off state by allowing input signals to escape to the high-frequency ground, thereby enhancing electrical isolation.
Implementation Method 1
the first switching circuit is formed using a parasitic diode formed at a junction surface between an N-well and the back gate
Implementation Method 2
by parasitic capacitance between the gate or back gate and source or drain of the FET itself, a potential at the gate or back gate can follow fluctuations over time in source or drain potential
Data Source
AI summary
An NMOS transistor performs electrical conduction or cut-off between a drain and a source by controlling a potential at a gate. A resistive element is connected between a back gate of the NMOS transistor and a high-frequency ground. A first switching circuit is disposed in parallel with the resistive element between the back gate and the high-frequency ground and causes a short circuit between the back gate and the high-frequency ground upon cut-off.