NMOS Sampling Switch Biasing for Below-Ground ADC Isolation
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Solution Overview
Problem
In analog-to-digital converters, sampling switches face challenges in remaining non-conductive during voltage swings that exceed the power supply voltage range, leading to inaccurate conversions if the pn junction diodes become forward-biased or a conductive channel forms.
Innovation Solution
A junction-isolated NMOS transistor sampling switch with a controller that biases the gate and p-well to exceed the power supply voltage range, ensuring the switch remains non-conductive by quickly switching the gate voltage from high to low power supply voltage and applying a low bias voltage to maintain isolation during analog-to-digital conversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a junction-isolated MOSFET transistor is used as a sampling switch, then the switch can be turned off quickly, but the pn junction diodes may become forward-biased during voltage swings exceeding power supply range, causing substantial conduction and inaccurate conversion
Solution Approach 1:
The patent applies preliminary anti-action by preemptively counteracting the forward bias condition of the pn junction diodes. A controller circuit generates a counter-voltage on the p-well that opposes the voltage swing on the drain or source, preventing the pn junction from becoming forward-biased. This counter-voltage is applied in advance and continuously during the voltage swing, ensuring the diode remains reverse-biased or at zero bias, thus preventing substantial conduction while maintaining fast switching capability.
Solution Approach 2:
The patent changes the voltage parameter of the p-well dynamically to maintain proper bias conditions. The controller circuit adjusts the p-well voltage based on the instantaneous voltage conditions during switching and voltage swings. By modulating the p-well voltage parameter, the system prevents the pn junction from entering the forward-bias region, thereby maintaining isolation accuracy during fast transitions and voltage swings that exceed the power supply range.
2Measurement precision
If the sampling switch is controlled to remain non-conductive during voltage swings beyond power supply range, then accurate analog-to-digital conversion is achieved, but the control circuit complexity increases
Solution Approach 1:
The patent introduces a p-well voltage controller as an intermediary element between the power supply and the MOSFET sampling switch. This controller circuit acts as a mediator that senses the voltage conditions and adjusts the p-well voltage accordingly to maintain proper biasing. The intermediary controller simplifies the overall control by providing automatic bias adjustment, ensuring the sampling switch remains non-conductive during voltage swings beyond the power supply range while achieving accurate analog-to-digital conversion without requiring complex external control mechanisms.
3Reliability
If a negative bias voltage is applied to the p-well to prevent forward biasing, then the sampling switch remains non-conductive, but the voltage range for accurate operation is limited
Solution Approach 1:
The patent transitions from a static negative bias voltage approach to a dynamic biasing scheme. The controller circuit continuously adjusts the p-well voltage based on the instantaneous voltage conditions during switching and signal swings. This dynamic adjustment allows the system to maintain proper isolation reliability during large voltage swings that exceed the power supply range, as the p-well voltage is modulated in real-time to counteract the voltage swings and prevent forward biasing, thereby extending the voltage range handling capability while maintaining isolation reliability.
Data Source
AI summary
In one embodiment, an A/D converter samples an analog input signal voltage by applying the input signal to a first capacitor terminal, while a second capacitor terminal is connected to ground via an NMOS sampling switch, to charge the capacitor to the input signal voltage. During an analog-to-digital conversion process, the second capacitor terminal may swing in a voltage range that extends below ground. A controller circuit provides bias voltage signals to a gate terminal and to a p-well of the NMOS sampling switch, to selectively turn the sampling switch on and off. In a first step of a multi-step sampling process, the controller very quickly discharges the gate terminal to ground to isolate a quantity of charge on the second capacitor plate. In a subsequent step of the sampling process, the controller circuit applies a negative voltage to the gate terminal and p-well to ensure that the quantity of change is substantially preserved during the ensuing analog-to-digital conversion process.