NMOS Protection Switch Layout for Precise Overcurrent Detection

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Solution Overview

Problem

Existing electronic systems lack efficient and compact switches for protecting against overvoltage and overcurrent, with a need for improved detection precision and compatibility with the protected devices.

Innovation Solution

A switch comprising NMOS-type transistors configured in reverse ohmic mode, utilizing a combination of high and low voltage transistors to detect and respond to overvoltage and overcurrent, integrated with control circuits for precise detection and disconnection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a single high-voltage transistor is used for protection, then the device can handle overvoltage conditions, but the detection precision for overcurrent is insufficient

Engineering Contradiction:
Improveprotection capabilityVSAvoidovercurrent detection precision
Core Design Contradiction:
ReliabilityVSMeasurement precision

Solution Approach 1:

The patent divides the protection function into multiple specialized transistors: a first high-voltage transistor for handling overvoltage conditions and second low-voltage transistors for precise overcurrent detection. This segmentation allows each transistor to be optimized for its specific function, resolving the contradiction between overall protection capability and detection precision.

Inventive Principle:
Principle #1Segmentation

2Measurement precision

If multiple transistors are used to improve detection precision, then the detection capability is enhanced, but the device dimensions increase

Engineering Contradiction:
Improveovercurrent detection precisionVSAvoiddevice dimensions
Core Design Contradiction:
Measurement precisionVSVolume of moving object

Solution Approach 1:

The patent applies local quality by using low-voltage transistors with smaller dimensions specifically for the overcurrent detection function, while the high-voltage transistor handles the bulk protection function. This allows the device to achieve enhanced detection precision without a proportional increase in overall device volume.

Inventive Principle:
Principle #3Local quality

3Adaptability or versatility

If high-voltage transistors are used for both protection and detection, then the protection range is expanded, but the compatibility with protected devices is reduced

Engineering Contradiction:
Improveprotection rangeVSAvoidcompatibility with protected device
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent segments the transistor functions by using a high-voltage transistor for broad protection coverage and low-voltage transistors for precise detection compatible with sensitive electronic devices. This segmentation allows the system to maintain both wide protection range and high compatibility with protected devices.

Inventive Principle:
Principle #1Segmentation

4Volume of moving object

If a compact switch design is used, then the device dimensions are reduced, but the detection precision and protection capability are compromised

Engineering Contradiction:
Improvedevice dimensionsVSAvoidprotection capability
Core Design Contradiction:
Volume of moving objectVSReliability

Solution Approach 1:

The patent uses low-voltage transistors with inherently smaller dimensions for detection functions, allowing compact overall device design while maintaining detection precision. The high-voltage transistor provides protection capability without requiring excessive space, as it operates in a different voltage regime with different dimensional requirements.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20260074505A1Protection switch
Publication Date: 2026.03.12 STMICROELECTRONICS INT NV
  • US20260074505A1 patent drawing
  • US20260074505A1 patent drawing
  • US20260074505A1 patent drawing

AI summary

The present disclosure relates to a switch for protecting against overvoltage and overcurrent, comprising: a first NMOS-type transistor suitable for receiving across its conduction terminals a first voltage; a second NMOS-type transistor comprising a source terminal coupled to a source terminal of the first transistor, and being suitable for receiving across its conduction terminals a second voltage less than the first voltage; and a third NMOS-type transistor comprising a source terminal coupled to a source terminal of the first transistor, and being suitable for receiving across its conduction terminals the second voltage.