NMOS Protective Switch Layout for Compact Overcurrent Sensing
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Solution Overview
Problem
Existing overvoltage and overcurrent protection devices are inefficient, lack compatibility with protected devices, and require larger sizes due to the use of high-voltage transistors for current detection.
Innovation Solution
A protective switch using a combination of high-voltage and low-voltage NMOS transistors, with low-voltage transistors operating in reverse ohmic mode for current detection, reducing the need for a high-voltage transistor for current sensing and minimizing switch size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high-voltage transistors are used for current detection, then overcurrent detection capability is achieved, but device size increases
Solution Approach 1:
The protection device is segmented into two functional parts: a high-voltage transistor (first transistor) for overvoltage protection and voltage blocking, and low-voltage transistors (second and third transistors) for current detection. This segmentation allows each component to be optimized for its specific function, enabling accurate overcurrent detection without requiring a large high-voltage transistor for sensing purposes.
Solution Approach 2:
Low-voltage transistors are introduced as intermediary sensing elements that work in conjunction with the high-voltage transistor. The second transistor detects overcurrent conditions while the third transistor provides a reference signal, allowing the high-voltage transistor to be sized for protection rather than sensing, thus reducing overall device size while maintaining detection accuracy.
2Reliability
If traditional protection devices are used, then overvoltage and overcurrent protection is provided, but compatibility with protected devices is poor
Solution Approach 1:
Each transistor in the circuit is assigned specific electrical characteristics matched to its functional role. The high-voltage transistor is designed with parameters optimized for blocking overvoltages, while the low-voltage transistors are designed with parameters optimized for current sensing in the protected device's operating range. This local optimization of electrical characteristics improves compatibility with a wider range of protected devices.
Solution Approach 2:
The invention utilizes different voltage and current parameters for different transistor stages. The high-voltage transistor operates with parameters suitable for surge protection (high breakdown voltage), while the low-voltage transistors operate with parameters matched to the protected device's normal operating conditions. This parameter differentiation enables the protection device to adapt to various protected devices without compromising either protection reliability or compatibility.
3Reliability
If conventional protection switches are used, then basic protection function is achieved, but efficiency is low
Solution Approach 1:
The protection switch dynamically transitions between different operational states based on detected conditions. The low-voltage transistors continuously monitor current and switch states rapidly in response to overcurrent conditions, while the high-voltage transistor responds to overvoltage conditions. This dynamic operation allows the device to provide efficient protection with minimal impact on normal device operation, improving overall protection efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides more efficient, accurate, and compact overvoltage and overcurrent protection, enhancing compatibility with protected devices and reducing the overall size of the protection mechanism.
Implementation Method 1
said second and third transistors operate in reverse ohmic mode
Data Source
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AI summary
This description relates to an overvoltage and overcurrent protection switch (210) comprising: - a first NMOS transistor (T211) adapted to receive a first voltage between its conduction terminals; - a second NMOS transistor (T212) comprising a source terminal connected to a source terminal of said first transistor (T211), and being adapted to receive a second voltage between its conduction terminals lower than the first voltage; and - a third NMOS transistor (T213) comprising a source terminal connected to a source terminal of said first transistor (T211), and being adapted to receive said second voltage between its conduction terminals.