Self-Gate Pumped NMOS Switch Using Parasitic Capacitance
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Solution Overview
Problem
High-frequency electronic switches face challenges due to parasitic junction and gate oxide capacitance, leading to high ON resistance and increased power consumption when using PMOS-NMOS combinations, which complicates the design of low resistance switches.
Innovation Solution
A self-gate pumped NMOS high-speed switch method utilizing a diode and additional transistors to bias the gate voltage, eliminating the need for complex charge pump circuits by leveraging parasitic capacitance for voltage adjustment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If PMOS-NMOS combination is used for high-frequency switching, then switching capability is improved, but power consumption increases and circuit complexity increases
Solution Approach 1:
The patent removes the PMOS transistor from the traditional PMOS-NMOS switch combination, retaining only the NMOS transistor. This extraction eliminates the need for complex dual-gate control while maintaining high-frequency switching capability through the remaining NMOS device, thereby reducing power consumption and circuit complexity.
Solution Approach 2:
The patent employs a self-gate pumping mechanism where the gate voltage of the NMOS transistor is dynamically adjusted using its own parasitic capacitance and a simple RC circuit. This self-service approach eliminates the need for external charge pumps or complex control circuits, reducing both power consumption and circuit complexity while maintaining effective high-frequency switching.
2Speed
If gate voltage pumping is implemented to compensate for removed PMOS, then switching performance is improved, but circuit complexity increases due to oscillators and charge pumps
Solution Approach 1:
The patent extracts and eliminates the complex gate voltage pumping circuits (oscillators, charge pumps) from the design. Instead, it uses a simple RC circuit combined with the inherent parasitic capacitance of the NMOS transistor to achieve the necessary gate voltage control, dramatically simplifying the overall circuit while maintaining high-frequency switching performance.
Solution Approach 2:
The patent implements self-gate pumping by utilizing the NMOS transistor's own parasitic capacitance as the pumping capacitor. The gate voltage is automatically adjusted through the interaction of the RC circuit and the transistor's intrinsic capacitance, eliminating the need for external active components and complex control logic.
3Use of energy by moving object
If parasitic capacitance is utilized for self-gate pumping, then power consumption is reduced, but control precision may be affected
Solution Approach 1:
The patent converts the harmful parasitic capacitance, which normally degrades high-frequency performance, into a beneficial element by using it as the pumping capacitor in the self-gate control mechanism. This approach reduces power consumption while maintaining adequate gate voltage control precision through the RC time constant design.
Solution Approach 2:
The patent adjusts the resistance and capacitance values in the RC circuit to optimize the gate voltage control characteristics. By carefully selecting these parameters, the system achieves both low power consumption and sufficient control precision for the intended application, balancing the trade-off between energy efficiency and voltage control accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption, increases bandwidth, and simplifies circuit design by self-adjusting the gate voltage based on input signals, effectively addressing the limitations of high-frequency switching.
Implementation Method 1
leveraging parasitic capacitance for voltage adjustment
Data Source
AI summary
A method and apparatus for self gate pumped NMOS high speed switch have been disclosed.