High-Voltage NMOS Transistors on N-Substrate ESD Protection
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Solution Overview
Problem
The integration of high withstanding-voltage NMOS transistors on N-type semiconductor substrates for semiconductor integrated circuit devices poses challenges due to the need for high-temperature long-time thermal treatment, leading to increased manufacturing time and costs, while also requiring a large area for resistance to breakdown due to heat generation and electrostatic discharge (ESD).
Innovation Solution
A semiconductor integrated circuit device configuration that includes N-channel and P-channel low withstanding-voltage MOS transistors, along with high withstanding-voltage NMOS transistors, formed using ion implantation and high-temperature thermal treatment, with specific impurity concentration and depth profiles to achieve resistance to ESD without increasing manufacturing time or costs, and utilizing a self-aligned twin-well process for cost reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-temperature long-time thermal treatment is used to form deep N-type low-concentration impurity regions, then resistance to breakdown due to heat generation and ESD is improved, but manufacturing time and costs increase
Solution Approach 1:
The patent applies preliminary action by forming the N-type low-concentration impurity region at a shallower depth before the final high-temperature thermal treatment. This preliminary positioning allows the subsequent thermal treatment to achieve the desired deep diffusion without requiring excessively long treatment times, as the impurity distribution is already optimally prepared in advance.
Solution Approach 2:
The patent employs parameter changes by optimizing the depth and concentration profile of the N-type low-concentration impurity region. By carefully controlling the impurity concentration (1×10^16 to 1×10^18 atoms/cm³) and depth (0.5 to 2.0 μm from surface), the design achieves effective ESD protection while minimizing the thermal treatment time required for diffusion.
2Reliability
If high-temperature long-time thermal treatment is used to form deep N-type low-concentration impurity regions, then resistance to breakdown due to heat generation and ESD is improved, but manufacturing costs increase
Solution Approach 1:
The patent applies preliminary action by forming the N-type low-concentration impurity region at a shallower depth before the final high-temperature thermal treatment. This preliminary positioning allows the subsequent thermal treatment to achieve the desired deep diffusion without requiring excessively long treatment times, as the impurity distribution is already optimally prepared in advance.
Solution Approach 2:
The patent employs parameter changes by optimizing the depth and concentration profile of the N-type low-concentration impurity region. By carefully controlling the impurity concentration (1×10^16 to 1×10^18 atoms/cm³) and depth (0.5 to 2.0 μm from surface), the design achieves effective ESD protection while minimizing the thermal treatment time required for diffusion.
3Reliability
If large area is allocated for high withstanding-voltage elements, then resistance to high voltage and ESD is improved, but device area and cost increase
Solution Approach 1:
The patent applies local quality by creating a specifically engineered N-type low-concentration impurity region with optimized characteristics (concentration of 1×10^16 to 1×10^18 atoms/cm³ at depth of 0.5 to 2.0 μm) in the drain region. This localized impurity distribution provides enhanced ESD protection and high-voltage resistance precisely where needed, without requiring the entire device area to be enlarged.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables the production of semiconductor integrated circuit devices that operate at high voltages (30 V or higher) with resistance to breakdown due to heat generation and ESD, while maintaining low manufacturing costs and time, by optimizing the impurity concentration and depth profiles of the N-type and P-type well regions.
Implementation Method 1
resistance to breakdown due to heat generation and electrostatic discharge (ESD)
Implementation Method 2
formed using ion implantation and high-temperature thermal treatment
Implementation Method 3
formed using ion implantation and high-temperature thermal treatment
Data Source
AI summary
Provided is a semiconductor integrated circuit device including a first N-channel type high withstanding-voltage MOS transistor and a second N-channel type high withstanding-voltage MOS transistor formed on an N-type semiconductor substrate, the first N-channel type high withstanding-voltage transistor including a third N-type low-concentration impurity region containing arsenic having a depth smaller than a P-type well region in a drain region within the P-type well region, and the second N-channel type high withstanding-voltage MOS transistor including a fourth N-type low-concentration impurity region that is adjacent to the P-type well region and has a bottom surface being in contact with the N-type semiconductor substrate. In this manner, the high withstanding-voltage NMOS transistors capable of operating at 30 V or higher are integrated on the N-type semiconductor substrate.