NMOS Transistor Segmentation in Level Shift Circuits
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Solution Overview
Problem
Conventional semiconductor devices with NMOS transistors in level shift circuits face issues with unnecessary current paths forming due to non-depleted regions in the N− epitaxial layer, leading to decreased resistance and impaired signal transmission, especially when multiple NMOS transistors are involved.
Innovation Solution
A semiconductor device configuration featuring a P type substrate with N− and P regions, where the NMOS transistors are surrounded by a P region and separated from the N− epitaxial layer, preventing unnecessary current paths by maintaining a potential barrier and ensuring stable signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If NMOS transistors are configured in a conventional planar structure with N- epitaxial layer, then the device can operate as a level shift circuit, but unnecessary current paths form through non-depleted regions causing signal transmission failure
Solution Approach 1:
The patent segments the N- epitaxial layer into multiple isolated N- regions (first N- region, second N- region, third N- region) separated by P regions. This segmentation prevents the formation of continuous non-depleted current paths that would otherwise connect different parts of the circuit, thereby eliminating the harmful current leakage while maintaining the level shift circuit functionality.
Solution Approach 2:
The patent extracts and removes the problematic continuous N- epitaxial layer structure that allows unwanted current flow. By replacing it with isolated N- regions embedded in P regions, the harmful current paths are taken out of the circuit while the essential transistor operation is preserved through the isolated N- regions.
2Ease of manufacture
If the N- epitaxial layer is used as a continuous substrate, then manufacturing is simplified, but resistance decreases when voltage decreases due to non-depleted regions forming current paths
Solution Approach 1:
The patent applies local quality by creating different structural configurations in different regions of the device. The N- regions are locally isolated within P regions rather than forming a continuous layer, which maintains manufacturing feasibility while ensuring that each local region maintains stable resistance characteristics independent of voltage changes.
3Productivity
If multiple NMOS transistors are formed in close proximity, then device integration is improved, but current leakage between transistors increases due to shared non-depleted regions
Solution Approach 1:
The patent segments the semiconductor structure by inserting P regions between adjacent N- regions containing NMOS transistors. This segmentation physically isolates the transistor regions, preventing current leakage between transistors while allowing them to be formed in close proximity for high integration density.
Solution Approach 2:
The P regions act as intermediary barriers between adjacent N- regions and NMOS transistors. These intermediary P regions block the formation of direct current paths between transistors, enabling high-density integration without the harmful inter-transistor current leakage that would occur with continuous N- regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively prevents current leakage and maintains signal integrity by ensuring the NMOS transistors operate within a stable potential barrier, even when voltage decreases, thus maintaining the effective resistance of the resistor and preventing signal disruption.
Implementation Method 1
the N− epitaxial layer 2 is depleted to produce a potential barrier of a depletion layer, which in turn cuts off an electron current
Data Source
AI summary
A semiconductor device that can prevent an unnecessary current path from being formed so that a normal signal is transmitted is provided. The semiconductor device comprises an N− region formed in a surface region of a P type substrate, a P region formed in the surface region, the P region included in the N− region or adjacent to the N− region, one or more semiconductor elements each of which has a first N type region and a second N type region formed in a portion of the P region, the first N type region and the second N type region being separated from each other, a first electrode formed on the first N type region, a second electrode formed on the second N type region, and a gate electrode formed over a surface of the P region between the first N type region and the second N type region. The first N type region and the second N type region are surrounded by the P region and separated from the N− region.