NMP DIMM Address Map Switching for Contiguous SRAM
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Solution Overview
Problem
The existing Near Memory Processing (NMP) dual in-line memory module (DIMM) experiences performance degradation due to a non-contiguous address map, caused by the host system treating static random-access memory (SRAM) as dynamic random-access memory (DRAM), leading to a large number of vacant spaces and inefficient memory allocation.
Innovation Solution
The NMP DIMM switches from a first address map used during interface training to a second address map for normal operation, eliminating the need for a look-up table and providing contiguous memory by adapting the address management to manage the SRAM space effectively, using an address management controller with a direct and adaptive address map controller to handle the switch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the host system treats SRAM as DRAM and prepares an address map by interleaving at rank, bank group, bank, row and column levels, then the address map can be created using standard DRAM protocols, but the address map includes a large number of vacant spaces causing non-contiguous memory which drastically slows performance
Solution Approach 1:
The patent implements a dynamic address map switching mechanism where the system transitions from a first address map (designed for DRAM compatibility with interleaving) to a second address map (optimized for SRAM contiguity) based on operational mode. During interface training, the first address map is used to maintain DRAM protocol compatibility, while during normal operation, the second address map provides contiguous memory access for optimal SRAM performance.
Solution Approach 2:
The patent changes the address mapping parameters dynamically based on operational phase. The address map configuration is altered from an interleaved structure (with vacant spaces) during training to a contiguous structure during normal operation, effectively changing the addressing parameters to match the physical characteristics of SRAM while maintaining protocol compatibility.
2Ease of operation
If the host system allocates memory space assuming SRAM is DRAM, then standard memory allocation protocols can be used, but the small size of SRAM relative to DRAM results in large vacant spaces in the address map
Solution Approach 1:
The patent introduces an address management controller as an intermediary between the host system and the SRAM. This controller translates host system memory allocation requests (based on DRAM assumptions) into appropriate SRAM address mappings, eliminating the need for the host system to understand SRAM's physical characteristics while maximizing effective memory utilization through contiguous addressing.
3Reliability
If the NMP DIMM uses a first address map during interface training, then proper interface initialization can be achieved, but switching to a second address map is needed for normal operation to eliminate vacant spaces
Solution Approach 1:
The patent performs preliminary interface training using the first address map before switching to the optimized second address map. This preliminary action ensures that the interface is properly initialized and trained with the DRAM-compatible address map, after which the system transitions to the more efficient contiguous address map for normal operations.
Data Source
AI summary
A Near Memory Processing (NMP) dual in-line memory module (DIMM) for managing an address map is provided. The NMP DIMM includes: a static random-access memory (SRAM) provided on a Double Data Rate (DDR) interface; and an address management controller coupled to the SRAM, and configured to control the NMP DIMM to: receive a first indication from a host system to perform interface training for operating an SRAM space; perform the interface training using a first address map based on the first indication; receive a second indication from the host system indicating completion of the interface training for operating the SRAM space; switch from the first address map to a second address map for operating the SRAM space in response based on the second indication; and operate the SRAM space using the second address map.