Near Memory Processing DIMMs for Direct DIMM-to-DIMM Data Transfer
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Solution Overview
Problem
Existing Dual In-line Memory Modules (DIMMs) experience significant CPU load and latency in data movement due to the need for data to traverse central processing units and memory controllers, especially when communicating between local and remote DIMMs.
Innovation Solution
Implementing Near Memory Processing (NMP) DIMMs with integrated processing nodes and ports that enable direct communication and data processing between DIMMs, reducing the reliance on CPU resources by allowing DIMMs to parse commands, identify dependencies, and process data independently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data movement between DIMMs goes through CPU and memory controllers, then data transfer can be achieved using existing infrastructure, but CPU load increases and latency is added
Solution Approach 1:
The patent introduces NMP DIMMs as intermediary devices that include onboard processing nodes to handle data processing tasks locally. These processing nodes act as mediators between the CPU and traditional DIMMs, enabling direct DIMM-to-DIMM communication and reducing the need for data to traverse through the CPU and memory controllers, thereby reducing CPU load and latency
2Adaptability or versatility
If data moves between local and remote DIMMs through CPUs and memory controllers of both hosts, then communication between distributed memory modules is enabled, but latency increases significantly
Solution Approach 1:
The patent extracts the processing functionality from the CPU and memory controller path by embedding processing nodes directly within the NMP DIMMs. This extraction enables local data processing and filtering at the DIMM level, allowing distributed DIMM communication to occur more directly without requiring all data to traverse through both hosts' CPUs and memory controllers, thereby reducing latency
3Adaptability or versatility
If traditional DIMM architecture is used, then system compatibility is maintained, but CPU processing cycles are consumed for data movement operations
Solution Approach 1:
The patent implements multi-functionality in the NMP DIMM design, which can operate in multiple modes: as traditional DIMMs for backward compatibility, and as intelligent storage devices with onboard processing capabilities. The processing nodes can handle various tasks including data filtering, aggregation, and direct DIMM-to-DIMM communication, allowing the system to maintain compatibility while reducing CPU involvement in data movement operations
Data Source
AI summary
A method for operating a Near Memory Processing (NMP) Dual In-line Memory Module (DIMM) for DIMM-to-DIMM communication is provided. The NMP DIMM includes one or more ports for communicative connection to other NMP DIMMs. The method includes parsing, by one NMP DIMM, a NMP command received from a processor of a host platform, identifying data dependencies on one or more other NMP DIMMs based on the parsing, establishing communication with the one or more other NMP DIMMs through one or more ports of the one NMP DIMM, receiving data from the one or more other NMP DIMMs through one or more ports of the one NMP DIMM, processing the NMP command using the data received from one of the one or more other NMP DIMMs and data present in the one NMP DIMM, and sending a NMP command completion notification to the processor of the host platform.